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| author | Andrew Waterman <andrew@sifive.com> | 2026-02-24 16:41:39 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2026-02-24 16:41:39 -0800 |
| commit | ae1531c207eccfe11d6009d39ab7998a93dfb139 (patch) | |
| tree | 7450d0244b3557a0d7220390789a54191ed5a48a /fdt | |
| parent | 68d45146859b51062f8464c4e82650ab52aa6233 (diff) | |
| parent | 114be91bbe7e907f1070d807ae56ce50993304f6 (diff) | |
| download | riscv-isa-sim-master.zip riscv-isa-sim-master.tar.gz riscv-isa-sim-master.tar.bz2 | |
Make minstretcfg/mcyclecfg privilege bits read-only zero as appropriate
Diffstat (limited to 'fdt')
0 files changed, 0 insertions, 0 deletions