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| author | Yunsup Lee <yunsup@cs.berkeley.edu> | 2011-04-09 20:18:04 -0700 |
|---|---|---|
| committer | Yunsup Lee <yunsup@cs.berkeley.edu> | 2011-04-09 20:18:36 -0700 |
| commit | 4b534147c0c49f9ea57f4c686af7c6508d114a99 (patch) | |
| tree | 2c905ba04c04f1f63a872d7e0b269c97197e7ebf /config.h.in | |
| parent | 7198e5091fa9d2606a993cae45f9c90e170f3103 (diff) | |
| download | riscv-isa-sim-4b534147c0c49f9ea57f4c686af7c6508d114a99.zip riscv-isa-sim-4b534147c0c49f9ea57f4c686af7c6508d114a99.tar.gz riscv-isa-sim-4b534147c0c49f9ea57f4c686af7c6508d114a99.tar.bz2 | |
[sim] add disable option for vector
Diffstat (limited to 'config.h.in')
| -rw-r--r-- | config.h.in | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/config.h.in b/config.h.in index fb0f56f..e592810 100644 --- a/config.h.in +++ b/config.h.in @@ -30,6 +30,9 @@ /* Define if instruction compression is supported */ #undef RISCV_ENABLE_RVC +/* Define if vector processor is supported */ +#undef RISCV_ENABLE_VEC + /* Define if libopcodes exists */ #undef RISCV_HAVE_LIBOPCODES |