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| author | Andrew Waterman <andrew@sifive.com> | 2024-10-18 17:43:22 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-10-18 17:43:22 -0700 |
| commit | 88fc84ded155a9e01987c4dfb7a77800e69b232b (patch) | |
| tree | aeeb7149578cfe11ca4ef65fec3c367b651b4e82 /arch_test_target/spike/device/rv64i_m/I | |
| parent | fa694e2ae3898c1906731dff3a50f7e660920f44 (diff) | |
| parent | 8566627eebc8d87c4090ea6f82cbf302144da020 (diff) | |
| download | riscv-isa-sim-master.zip riscv-isa-sim-master.tar.gz riscv-isa-sim-master.tar.bz2 | |
add missing sdt/sie interaction when writing mstatus directly
Diffstat (limited to 'arch_test_target/spike/device/rv64i_m/I')
0 files changed, 0 insertions, 0 deletions