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| author | Andrew Waterman <andrew@sifive.com> | 2020-02-10 20:45:20 -0600 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-02-10 20:45:20 -0600 |
| commit | ab141b814daf778597b106c155fd8c011be90f10 (patch) | |
| tree | 8c797e00e0a855ad2c46b501fcfe88f49a6923a1 /VERSION | |
| parent | 60698a4a66edd7011d054be27fa30efd7aabee3e (diff) | |
| parent | 6b90a455dc185d25a7cdd69b89d7b43cfbd43751 (diff) | |
| download | riscv-isa-sim-ab141b814daf778597b106c155fd8c011be90f10.zip riscv-isa-sim-ab141b814daf778597b106c155fd8c011be90f10.tar.gz riscv-isa-sim-ab141b814daf778597b106c155fd8c011be90f10.tar.bz2 | |
Merge pull request #392 from riscv/fesvr-no-dm-when-dmactive-0
FESVR: Can't read a DM register when DMACTIVE=0
Diffstat (limited to 'VERSION')
0 files changed, 0 insertions, 0 deletions