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| author | Daniel Lustig <dlustig@nvidia.com> | 2021-02-08 17:21:32 -0500 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-02-08 14:21:32 -0800 |
| commit | 3887f46243bd8ddab7073b2b3a4317301673ab9b (patch) | |
| tree | 3b9f1fab1cf29613e7694d69eb2b4e3bcbb25158 /README.md | |
| parent | 86ab921adfcd337bcc105e265597aba5d3249436 (diff) | |
| download | riscv-isa-sim-3887f46243bd8ddab7073b2b3a4317301673ab9b.zip riscv-isa-sim-3887f46243bd8ddab7073b2b3a4317301673ab9b.tar.gz riscv-isa-sim-3887f46243bd8ddab7073b2b3a4317301673ab9b.tar.bz2 | |
Zsn has been renamed Svnapot (#641)
Diffstat (limited to 'README.md')
| -rw-r--r-- | README.md | 2 |
1 files changed, 1 insertions, 1 deletions
@@ -25,7 +25,7 @@ Spike supports the following RISC-V ISA features: - Conformance to both RVWMO and RVTSO (Spike is sequentially consistent) - Machine, Supervisor, and User modes, v1.11 - Hypervisor extension, v0.6.1 - - Zsn extension, v0.1 + - Svnapot extension, v0.1 - Debug v0.14 Versioning and APIs |