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| author | Andrew Waterman <andrew@sifive.com> | 2020-02-11 15:20:44 -0600 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-02-11 15:20:44 -0600 |
| commit | 78344a5a2c88c4c313b8b216bd76f31792812205 (patch) | |
| tree | 6d1a7c0bfd88f2d96b4e8efdb9a7d762837eeb24 /LICENSE | |
| parent | ab141b814daf778597b106c155fd8c011be90f10 (diff) | |
| parent | b8eb9cd50da527d8ac280f818baa5473ab21da91 (diff) | |
| download | riscv-isa-sim-78344a5a2c88c4c313b8b216bd76f31792812205.zip riscv-isa-sim-78344a5a2c88c4c313b8b216bd76f31792812205.tar.gz riscv-isa-sim-78344a5a2c88c4c313b8b216bd76f31792812205.tar.bz2 | |
Merge pull request #393 from riscv/fesvr-dmactive-before-read
FESVR: ensure dmactive is 1 before reading debug module registers
Diffstat (limited to 'LICENSE')
0 files changed, 0 insertions, 0 deletions