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author | Andrew Waterman <andrew@sifive.com> | 2019-12-16 12:55:24 -0800 |
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committer | Andrew Waterman <andrew@sifive.com> | 2019-12-16 12:55:24 -0800 |
commit | fd89bebdbaaf651ed20ea7d788747ff6cf1d82ae (patch) | |
tree | f19a8a092e8bf122dc56a62ef7a5f245737e7df8 | |
parent | 66cf3792349d4745c9e204f255653eb1f4e8b99c (diff) | |
download | riscv-isa-sim-fd89bebdbaaf651ed20ea7d788747ff6cf1d82ae.zip riscv-isa-sim-fd89bebdbaaf651ed20ea7d788747ff6cf1d82ae.tar.gz riscv-isa-sim-fd89bebdbaaf651ed20ea7d788747ff6cf1d82ae.tar.bz2 |
Fix first-fault load exception behavior
First-fault loads should only trap on the zeroth element; traps detected
on later elements should just reduce vl.
-rw-r--r-- | riscv/decode.h | 16 |
1 files changed, 13 insertions, 3 deletions
diff --git a/riscv/decode.h b/riscv/decode.h index f0d8172..e9d3a9a 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -1468,12 +1468,23 @@ for (reg_t i = 0; i < vlmax; ++i) { \ bool early_stop = false; \ const reg_t vlmax = P.VU.vlmax; \ const reg_t vlmul = P.VU.vlmul; \ + p->VU.vstart = 0; \ for (reg_t i = 0; i < vlmax && vl != 0; ++i) { \ VI_STRIP(i); \ VI_ELEMENT_SKIP(i); \ \ for (reg_t fn = 0; fn < nf; ++fn) { \ - itype##64_t val = MMU.load_##itype##tsew(baseAddr + (i * nf + fn) * (tsew / 8)); \ + itype##64_t val; \ + try { \ + val = MMU.load_##itype##tsew(baseAddr + (i * nf + fn) * (tsew / 8)); \ + } catch (trap_t& t) { \ + if (i == 0) \ + throw t; /* Only take exception on zeroth element */ \ + /* Reduce VL if an exception occurs on a later element */ \ + early_stop = true; \ + P.VU.vl = i; \ + break; \ + } \ \ switch (sew) { \ case e8: \ @@ -1494,8 +1505,7 @@ for (reg_t i = 0; i < vlmax; ++i) { \ if (early_stop) { \ break; \ } \ - } \ - p->VU.vstart = 0; + } // |