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author | Andrew Waterman <andrew@sifive.com> | 2019-12-16 12:46:20 -0800 |
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committer | Andrew Waterman <andrew@sifive.com> | 2019-12-16 12:46:20 -0800 |
commit | 66cf3792349d4745c9e204f255653eb1f4e8b99c (patch) | |
tree | 948a3743087acbaa22de6df1e21a0ea71a1d5632 | |
parent | 33a9196161fd62facee59feac8b70b37ad76faca (diff) | |
download | riscv-isa-sim-66cf3792349d4745c9e204f255653eb1f4e8b99c.zip riscv-isa-sim-66cf3792349d4745c9e204f255653eb1f4e8b99c.tar.gz riscv-isa-sim-66cf3792349d4745c9e204f255653eb1f4e8b99c.tar.bz2 |
Simplify vleff.v implementation in the same way as vle.v
-rw-r--r-- | riscv/insns/vleff_v.h | 64 |
1 files changed, 11 insertions, 53 deletions
diff --git a/riscv/insns/vleff_v.h b/riscv/insns/vleff_v.h index e858de9..af3aa25 100644 --- a/riscv/insns/vleff_v.h +++ b/riscv/insns/vleff_v.h @@ -1,54 +1,12 @@ -require(P.VU.vsew >= e8 && P.VU.vsew <= e64); -const reg_t nf = insn.v_nf() + 1; -require((nf * P.VU.vlmul) <= (NVPR / 4)); -VI_CHECK_SXX; -const reg_t sew = P.VU.vsew; -const reg_t vl = P.VU.vl; -const reg_t baseAddr = RS1; -const reg_t rd_num = insn.rd(); -bool early_stop = false; -const reg_t vlmul = P.VU.vlmul; -for (reg_t i = 0; i < P.VU.vlmax && vl != 0; ++i) { - bool is_zero = false; - VI_STRIP(i); - VI_ELEMENT_SKIP(i); - - for (reg_t fn = 0; fn < nf; ++fn) { - MMU.load_uint8(baseAddr + (i * nf + fn) * 1); - - switch (sew) { - case e8: - P.VU.elt<uint8_t>(rd_num + fn * vlmul, vreg_inx) = - MMU.load_uint8(baseAddr + (i * nf + fn) * 1); - is_zero = P.VU.elt<uint8_t>(rd_num + fn * vlmul, vreg_inx) == 0; - break; - case e16: - P.VU.elt<uint16_t>(rd_num + fn * vlmul, vreg_inx) = - MMU.load_uint16(baseAddr + (i * nf + fn) * 2); - is_zero = P.VU.elt<uint16_t>(rd_num + fn * vlmul, vreg_inx) == 0; - break; - case e32: - P.VU.elt<uint32_t>(rd_num + fn * vlmul, vreg_inx) = - MMU.load_uint32(baseAddr + (i * nf + fn) * 4); - is_zero = P.VU.elt<uint32_t>(rd_num + fn * vlmul, vreg_inx) == 0; - break; - case e64: - P.VU.elt<uint64_t>(rd_num + fn * vlmul, vreg_inx) = - MMU.load_uint64(baseAddr + (i * nf + fn) * 8); - is_zero = P.VU.elt<uint64_t>(rd_num + fn * vlmul, vreg_inx) == 0; - break; - } - - if (is_zero) { - P.VU.vl = i; - early_stop = true; - break; - } - } - - if (early_stop) { - break; - } +// vle.v and vlseg[2-8]e.v +reg_t sew = P.VU.vsew; + +if (sew == e8) { + VI_LDST_FF(int, 8); +} else if (sew == e16) { + VI_LDST_FF(int, 16); +} else if (sew == e32) { + VI_LDST_FF(int, 32); +} else if (sew == e64) { + VI_LDST_FF(int, 64); } - -P.VU.vstart = 0; |