aboutsummaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorChih-Min Chao <chihmin.chao@sifive.com>2020-11-04 22:24:13 -0800
committerChih-Min Chao <chihmin.chao@sifive.com>2020-11-11 18:40:50 -0800
commitad8ef88a22533e5e31ffaff9c64ecd7853a51555 (patch)
tree33cf57bff44d4aac97e6d7889bebfe91ec369fb7
parent956ef9ac3a66d2d6cda5df33a0e3f1c7d57ed0e0 (diff)
downloadriscv-isa-sim-ad8ef88a22533e5e31ffaff9c64ecd7853a51555.zip
riscv-isa-sim-ad8ef88a22533e5e31ffaff9c64ecd7853a51555.tar.gz
riscv-isa-sim-ad8ef88a22533e5e31ffaff9c64ecd7853a51555.tar.bz2
mmu: add impl table and set function
some features are optional to u-arch or could be selectively supported. Add an impl_table to keep implemented feature Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
-rw-r--r--riscv/decode.h1
-rw-r--r--riscv/processor.cc33
-rw-r--r--riscv/processor.h14
3 files changed, 47 insertions, 1 deletions
diff --git a/riscv/decode.h b/riscv/decode.h
index b4bb2e6..98d9dea 100644
--- a/riscv/decode.h
+++ b/riscv/decode.h
@@ -236,6 +236,7 @@ private:
#define require_rv64 require(xlen == 64)
#define require_rv32 require(xlen == 32)
#define require_extension(s) require(p->supports_extension(s))
+#define require_impl(s) require(p->supports_impl(s))
#define require_fp require((STATE.mstatus & MSTATUS_FS) != 0)
#define require_accelerator require((STATE.mstatus & MSTATUS_XS) != 0)
diff --git a/riscv/processor.cc b/riscv/processor.cc
index b61bd33..28e16dd 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -27,7 +27,7 @@ processor_t::processor_t(const char* isa, const char* priv, const char* varch,
: debug(false), halt_request(HR_NONE), sim(sim), ext(NULL), id(id), xlen(0),
histogram_enabled(false), log_commits_enabled(false),
log_file(log_file), halt_on_reset(halt_on_reset),
- extension_table(256, false), last_pc(1), executions(1)
+ extension_table(256, false), impl_table(256, false), last_pc(1), executions(1)
{
VU.p = this;
@@ -45,6 +45,12 @@ processor_t::processor_t(const char* isa, const char* priv, const char* varch,
set_pmp_granularity(1 << PMP_SHIFT);
set_pmp_num(state.max_pmp);
+
+ if (max_xlen == 32)
+ set_mmu_capability(IMPL_MMU_SV32);
+ else if (max_xlen == 64)
+ set_mmu_capability(IMPL_MMU_SV48);
+
reset();
}
@@ -502,6 +508,31 @@ void processor_t::set_pmp_granularity(reg_t gran) {
lg_pmp_granularity = ctz(gran);
}
+void processor_t::set_mmu_capability(int cap)
+{
+ switch (cap) {
+ case IMPL_MMU_SV32:
+ set_impl(cap, true);
+ set_impl(IMPL_MMU, true);
+ break;
+ case IMPL_MMU_SV39:
+ set_impl(cap, true);
+ set_impl(IMPL_MMU, true);
+ break;
+ case IMPL_MMU_SV48:
+ set_impl(cap, true);
+ set_impl(IMPL_MMU_SV39, true);
+ set_impl(IMPL_MMU, true);
+ break;
+ default:
+ set_impl(IMPL_MMU_SV32, false);
+ set_impl(IMPL_MMU_SV39, false);
+ set_impl(IMPL_MMU_SV48, false);
+ set_impl(IMPL_MMU, false);
+ break;
+ }
+}
+
void processor_t::take_interrupt(reg_t pending_interrupts)
{
reg_t enabled_interrupts, deleg, status, mie, m_enabled;
diff --git a/riscv/processor.h b/riscv/processor.h
index 2187608..5e75e2f 100644
--- a/riscv/processor.h
+++ b/riscv/processor.h
@@ -245,6 +245,14 @@ typedef enum {
EXT_ZVEDIV,
} isa_extension_t;
+typedef enum {
+ IMPL_MMU_SV32,
+ IMPL_MMU_SV39,
+ IMPL_MMU_SV48,
+ IMPL_MMU_BARE,
+ IMPL_MMU,
+} impl_extension_t;
+
// Count number of contiguous 1 bits starting from the LSB.
static int cto(reg_t val)
{
@@ -292,6 +300,10 @@ public:
else
return extension_table[ext];
}
+ void set_impl(uint8_t impl, bool val) { impl_table[impl] = val; }
+ bool supports_impl(uint8_t impl) const {
+ return impl_table[impl];
+ }
reg_t pc_alignment_mask() {
return ~(reg_t)(supports_extension('C') ? 0 : 2);
}
@@ -409,6 +421,7 @@ public:
void set_pmp_num(reg_t pmp_num);
void set_pmp_granularity(reg_t pmp_granularity);
+ void set_mmu_capability(int cap);
const char* get_symbol(uint64_t addr);
@@ -428,6 +441,7 @@ private:
FILE *log_file;
bool halt_on_reset;
std::vector<bool> extension_table;
+ std::vector<bool> impl_table;
std::vector<insn_desc_t> instructions;