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author | Andrew Waterman <andrew@sifive.com> | 2020-11-09 15:10:41 -0800 |
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committer | Andrew Waterman <andrew@sifive.com> | 2020-11-09 15:10:41 -0800 |
commit | 956ef9ac3a66d2d6cda5df33a0e3f1c7d57ed0e0 (patch) | |
tree | 33324067f650a9c7c9fb43a1a141bbbbfc34c16d | |
parent | 6fe352d543df80a74a97a0cc6f0eeb58aada3dab (diff) | |
download | riscv-isa-sim-956ef9ac3a66d2d6cda5df33a0e3f1c7d57ed0e0.zip riscv-isa-sim-956ef9ac3a66d2d6cda5df33a0e3f1c7d57ed0e0.tar.gz riscv-isa-sim-956ef9ac3a66d2d6cda5df33a0e3f1c7d57ed0e0.tar.bz2 |
Update readme to reflect bi-endian support
-rw-r--r-- | README.md | 1 |
1 files changed, 1 insertions, 0 deletions
@@ -20,6 +20,7 @@ Spike supports the following RISC-V ISA features: - C extension, v2.0 - B extension, v0.92 - V extension, v0.9, w/ Zvlsseg/Zvamo/Zvqmac, w/o Zvediv, (_requires a 64-bit host_) + - Bi-endianness - Conformance to both RVWMO and RVTSO (Spike is sequentially consistent) - Machine, Supervisor, and User modes, v1.11 - Debug v0.14 |