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| author | Ved Shanbhogue <ved@rivosinc.com> | 2024-09-12 19:37:26 -0500 |
|---|---|---|
| committer | Ved Shanbhogue <ved@rivosinc.com> | 2024-09-17 21:23:36 -0500 |
| commit | a8525b62430432c020bd01f1ce51d10f36cc8da3 (patch) | |
| tree | 280ed9f9a8df415d92e40dfda2f1864b9ab244ce | |
| parent | 2e816f23cba244abe9201ba22dc2b4a891e63264 (diff) | |
| download | riscv-isa-sim-a8525b62430432c020bd01f1ce51d10f36cc8da3.zip riscv-isa-sim-a8525b62430432c020bd01f1ce51d10f36cc8da3.tar.gz riscv-isa-sim-a8525b62430432c020bd01f1ce51d10f36cc8da3.tar.bz2 | |
fix error in reading right sstatus
| -rw-r--r-- | riscv/processor.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/processor.cc b/riscv/processor.cc index 60f6a89..c4d8c06 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -446,7 +446,7 @@ void processor_t::take_trap(trap_t& t, reg_t epc) // An unexpected trap - a trap when SDT is 1 - traps to M-mode if ((state.prv <= PRV_S && bit < max_xlen) && (((vsdeleg >> bit) & 1) || ((hsdeleg >> bit) & 1))) { - reg_t s = curr_virt ? state.nonvirtual_sstatus->read() : state.sstatus->read(); + reg_t s = state.sstatus->read(); supv_double_trap = get_field(s, MSTATUS_SDT); if (supv_double_trap) vsdeleg = hsdeleg = 0; |