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-rw-r--r--riscv/processor.cc2
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/processor.cc b/riscv/processor.cc
index 60f6a89..c4d8c06 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -446,7 +446,7 @@ void processor_t::take_trap(trap_t& t, reg_t epc)
// An unexpected trap - a trap when SDT is 1 - traps to M-mode
if ((state.prv <= PRV_S && bit < max_xlen) &&
(((vsdeleg >> bit) & 1) || ((hsdeleg >> bit) & 1))) {
- reg_t s = curr_virt ? state.nonvirtual_sstatus->read() : state.sstatus->read();
+ reg_t s = state.sstatus->read();
supv_double_trap = get_field(s, MSTATUS_SDT);
if (supv_double_trap)
vsdeleg = hsdeleg = 0;