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| author | Andrew Waterman <andrew@sifive.com> | 2019-11-12 18:36:32 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2019-11-12 18:36:32 -0800 |
| commit | 9b06f14085396b99c2a7e33cac8be8ee54948a52 (patch) | |
| tree | 6d6054c9abd3349a07ab59fc0fc6724e77881f78 | |
| parent | f29ea12a7714290ee993347b55aca5c9b14cd217 (diff) | |
| download | riscv-isa-sim-9b06f14085396b99c2a7e33cac8be8ee54948a52.zip riscv-isa-sim-9b06f14085396b99c2a7e33cac8be8ee54948a52.tar.gz riscv-isa-sim-9b06f14085396b99c2a7e33cac8be8ee54948a52.tar.bz2 | |
Fix mode-transition logic when S-mode not present
| -rw-r--r-- | riscv/processor.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/processor.cc b/riscv/processor.cc index 7881484..888d1a4 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -376,7 +376,7 @@ reg_t processor_t::legalize_privilege(reg_t prv) if (!supports_extension('U')) return PRV_M; - if (prv == PRV_H || !supports_extension('S')) + if (prv == PRV_H || (prv == PRV_S && !supports_extension('S'))) return PRV_U; return prv; |