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| author | Andrew Waterman <andrew@sifive.com> | 2019-11-12 18:35:52 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2019-11-12 18:35:52 -0800 |
| commit | f29ea12a7714290ee993347b55aca5c9b14cd217 (patch) | |
| tree | bcd2d4dfdbc1f244d12965e61bba9615da24ce73 | |
| parent | 4b7e763d246b130a204e9068b692f1db7d17fb68 (diff) | |
| download | riscv-isa-sim-f29ea12a7714290ee993347b55aca5c9b14cd217.zip riscv-isa-sim-f29ea12a7714290ee993347b55aca5c9b14cd217.tar.gz riscv-isa-sim-f29ea12a7714290ee993347b55aca5c9b14cd217.tar.bz2 | |
SRET requires S-mode
| -rw-r--r-- | riscv/insns/sret.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/riscv/insns/sret.h b/riscv/insns/sret.h index ae841de..be837a3 100644 --- a/riscv/insns/sret.h +++ b/riscv/insns/sret.h @@ -1,3 +1,4 @@ +require_extension('S'); require_privilege(get_field(STATE.mstatus, MSTATUS_TSR) ? PRV_M : PRV_S); set_pc_and_serialize(p->get_state()->sepc); reg_t s = STATE.mstatus; |