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| author | Andrew Waterman <andrew@sifive.com> | 2019-12-16 12:21:44 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2019-12-16 12:22:03 -0800 |
| commit | 33a9196161fd62facee59feac8b70b37ad76faca (patch) | |
| tree | 4d7871fc042177bcd4af00e0d4dc5d3363ee3418 | |
| parent | e3cc8b69d101921a836ca76f67b6bb032ecc3d11 (diff) | |
| download | riscv-isa-sim-33a9196161fd62facee59feac8b70b37ad76faca.zip riscv-isa-sim-33a9196161fd62facee59feac8b70b37ad76faca.tar.gz riscv-isa-sim-33a9196161fd62facee59feac8b70b37ad76faca.tar.bz2 | |
Don't terminate first-fault loads on zero data values
| -rw-r--r-- | riscv/decode.h | 6 |
1 files changed, 0 insertions, 6 deletions
diff --git a/riscv/decode.h b/riscv/decode.h index f8ac020..f0d8172 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -1489,12 +1489,6 @@ for (reg_t i = 0; i < vlmax; ++i) { \ p->VU.elt<uint64_t>(rd_num + fn * vlmul, vreg_inx) = val; \ break; \ } \ - \ - if (val == 0) { \ - p->VU.vl = i; \ - early_stop = true; \ - break; \ - } \ } \ \ if (early_stop) { \ |