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author | Megan Wachs <megan@sifive.com> | 2018-04-30 12:07:48 -0700 |
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committer | Megan Wachs <megan@sifive.com> | 2018-04-30 12:07:48 -0700 |
commit | cc6a9c97e2834c272e3df8544f8eb465032212db (patch) | |
tree | 92d08ee86afcbbe56a963cb82007f37b349f5eb1 | |
parent | c0172e96bc2e83c990a22342ce7e99ba73142c47 (diff) | |
download | riscv-isa-sim-tweak_debug_rom.zip riscv-isa-sim-tweak_debug_rom.tar.gz riscv-isa-sim-tweak_debug_rom.tar.bz2 |
Debug ROM: Adjust debug ROM to have fewer icache flushestweak_debug_rom
-rwxr-xr-x | debug_rom/debug_rom.S | 25 |
1 files changed, 12 insertions, 13 deletions
diff --git a/debug_rom/debug_rom.S b/debug_rom/debug_rom.S index 28c7076..d5435cc 100755 --- a/debug_rom/debug_rom.S +++ b/debug_rom/debug_rom.S @@ -32,33 +32,32 @@ entry_loop: csrr s0, CSR_MHARTID sw s0, DEBUG_ROM_HALTED(zero) lbu s0, DEBUG_ROM_FLAGS(s0) // 1 byte flag per hart. Only one hart advances here. - andi s0, s0, (1 << DEBUG_ROM_FLAG_GO) - bnez s0, going - csrr s0, CSR_MHARTID - lbu s0, DEBUG_ROM_FLAGS(s0) // multiple harts can resume here - andi s0, s0, (1 << DEBUG_ROM_FLAG_RESUME) - bnez s0, resume - jal zero, entry_loop + andi s0, s0, (1 << DEBUG_ROM_FLAG_GO) | (1 << DEBUG_ROM_FLAG_RESUME) + beqz s0, entry_loop // Loop until either GO or RESUME is set. -_exception: - sw zero, DEBUG_ROM_EXCEPTION(zero) // Let debug module know you got an exception. - ebreak + andi s0, s0, (1 << DEBUG_ROM_FLAG_GO) + beqz s0, _resume // If GO is clear at this point, RESUME must be set. -going: - csrr s0, CSR_DSCRATCH // Restore s0 here - sw zero, DEBUG_ROM_GOING(zero) // When debug module sees this write, the GO flag is reset. + csrr s0, CSR_DSCRATCH // Restore s0 here + sw zero, DEBUG_ROM_GOING(zero) // When debug module sees this write, the GO flag is reset. fence fence.i jalr zero, zero, %lo(whereto) // Debug module will put different instructions and data in the RAM, // so we use fence and fence.i for safety. (rocket-chip doesn't have this // because jalr is special there) + + _resume: csrr s0, CSR_MHARTID sw s0, DEBUG_ROM_RESUMING(zero) // When Debug Module sees this write, the RESUME flag is reset. csrr s0, CSR_DSCRATCH // Restore s0 dret +_exception: + sw zero, DEBUG_ROM_EXCEPTION(zero) // Let debug module know you got an exception. + ebreak + // END OF ACTUAL "ROM" CONTENTS. BELOW IS JUST FOR LINKER SCRIPT. .section .whereto |