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| author | Andrew Waterman <andrew@sifive.com> | 2022-12-29 15:38:37 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2023-01-03 16:44:42 -0800 |
| commit | a11af65d0e30cd41fa25980686be701adcbb8ee0 (patch) | |
| tree | 019b1f9bab166f64e6bb04b4082839356906b0d6 | |
| parent | 8d084dbd092a916a2c26d9cb7f30d5651aa3181b (diff) | |
| download | riscv-isa-sim-a11af65d0e30cd41fa25980686be701adcbb8ee0.zip riscv-isa-sim-a11af65d0e30cd41fa25980686be701adcbb8ee0.tar.gz riscv-isa-sim-a11af65d0e30cd41fa25980686be701adcbb8ee0.tar.bz2 | |
Add --[no-]misaligned command-line options
They don't do anything yet.
| -rw-r--r-- | ci-tests/testlib.c | 1 | ||||
| -rw-r--r-- | riscv/cfg.h | 3 | ||||
| -rw-r--r-- | spike_main/spike-log-parser.cc | 1 | ||||
| -rw-r--r-- | spike_main/spike.cc | 3 |
4 files changed, 8 insertions, 0 deletions
diff --git a/ci-tests/testlib.c b/ci-tests/testlib.c index 3d2d18d..e9b7daa 100644 --- a/ci-tests/testlib.c +++ b/ci-tests/testlib.c @@ -21,6 +21,7 @@ int main() "rv64gcv", "MSU", "vlen:128,elen:64", + false, endianness_little, 16, mem_cfg, diff --git a/riscv/cfg.h b/riscv/cfg.h index 88d7fa1..1b09f65 100644 --- a/riscv/cfg.h +++ b/riscv/cfg.h @@ -52,6 +52,7 @@ public: const char *default_bootargs, const char *default_isa, const char *default_priv, const char *default_varch, + const bool default_misaligned, const endianness_t default_endianness, const reg_t default_pmpregions, const std::vector<mem_cfg_t> &default_mem_layout, @@ -62,6 +63,7 @@ public: isa(default_isa), priv(default_priv), varch(default_varch), + misaligned(default_misaligned), endianness(default_endianness), pmpregions(default_pmpregions), mem_layout(default_mem_layout), @@ -75,6 +77,7 @@ public: cfg_arg_t<const char *> isa; cfg_arg_t<const char *> priv; cfg_arg_t<const char *> varch; + bool misaligned; endianness_t endianness; reg_t pmpregions; cfg_arg_t<std::vector<mem_cfg_t>> mem_layout; diff --git a/spike_main/spike-log-parser.cc b/spike_main/spike-log-parser.cc index 111e0db..41642a6 100644 --- a/spike_main/spike-log-parser.cc +++ b/spike_main/spike-log-parser.cc @@ -33,6 +33,7 @@ int main(int UNUSED argc, char** argv) /*default_isa=*/DEFAULT_ISA, /*default_priv=*/DEFAULT_PRIV, /*default_varch=*/DEFAULT_VARCH, + /*default_misaligned=*/false, /*default_endianness*/endianness_little, /*default_pmpregions=*/16, /*default_mem_layout=*/std::vector<mem_cfg_t>(), diff --git a/spike_main/spike.cc b/spike_main/spike.cc index b204091..f517ad3 100644 --- a/spike_main/spike.cc +++ b/spike_main/spike.cc @@ -49,6 +49,7 @@ static void help(int exit_code = 1) fprintf(stderr, " --dc=<S>:<W>:<B> W ways, and B-byte blocks (with S and\n"); fprintf(stderr, " --l2=<S>:<W>:<B> B both powers of 2).\n"); fprintf(stderr, " --big-endian Use a big-endian memory system.\n"); + fprintf(stderr, " --misaligned Support misaligned memory accesses\n"); fprintf(stderr, " --device=<P,B,A> Attach MMIO plugin device from an --extlib library\n"); fprintf(stderr, " P -- Name of the MMIO plugin\n"); fprintf(stderr, " B -- Base memory address of the device\n"); @@ -327,6 +328,7 @@ int main(int argc, char** argv) /*default_isa=*/DEFAULT_ISA, /*default_priv=*/DEFAULT_PRIV, /*default_varch=*/DEFAULT_VARCH, + /*default_misaligned=*/false, /*default_endianness*/endianness_little, /*default_pmpregions=*/16, /*default_mem_layout=*/parse_mem_layout("2048"), @@ -399,6 +401,7 @@ int main(int argc, char** argv) parser.option(0, "dc", 1, [&](const char* s){dc.reset(new dcache_sim_t(s));}); parser.option(0, "l2", 1, [&](const char* s){l2.reset(cache_sim_t::construct(s, "L2$"));}); parser.option(0, "big-endian", 0, [&](const char UNUSED *s){cfg.endianness = endianness_big;}); + parser.option(0, "misaligned", 0, [&](const char UNUSED *s){cfg.misaligned = true;}); parser.option(0, "log-cache-miss", 0, [&](const char UNUSED *s){log_cache = true;}); parser.option(0, "isa", 1, [&](const char* s){cfg.isa = s;}); parser.option(0, "pmpregions", 1, [&](const char* s){cfg.pmpregions = atoul_safe(s);}); |