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2025-10-28lib: sbi: Add SiFive proprietary xsfceaseNick Hu1-0/+2
Using ISA string "xsfcease" to detect the support of the custom instruction "CEASE". Reviewed-by: Cyan Yang <cyan.yang@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Nick Hu <nick.hu@sifive.com> Link: https://lore.kernel.org/r/20251020-cache-upstream-v7-6-69a132447d8a@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-10-28lib: sbi: Add SiFive proprietary xsfcflushdloneNick Hu1-0/+2
Using ISA string "xsfcflushdlone" to detect the support of the SiFive L1D cache flush custom instruction. Reviewed-by: Cyan Yang <cyan.yang@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Nick Hu <nick.hu@sifive.com> Link: https://lore.kernel.org/r/20251020-cache-upstream-v7-5-69a132447d8a@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-10-28lib: utils/cache: Add fdt cmo helpersNick Hu1-0/+40
Add the helpers to build up the cache hierarchy via FDT and provide some cmo functions for the user who want to flush the entire cache. Signed-off-by: Nick Hu <nick.hu@sifive.com> Reviewed-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251020-cache-upstream-v7-4-69a132447d8a@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-10-28lib: utils: Add FDT cache libraryNick Hu1-0/+34
Add the FDT cache library so we can build up the cache topology via the 'next-level-cache' DT property. Co-developed-by: Vincent Chen <vincent.chen@sifive.com> Signed-off-by: Vincent Chen <vincent.chen@sifive.com> Co-developed-by: Andy Chiu <andy.chiu@sifive.com> Signed-off-by: Andy Chiu <andy.chiu@sifive.com> Signed-off-by: Nick Hu <nick.hu@sifive.com> Reviewed-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251020-cache-upstream-v7-2-69a132447d8a@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-10-28lib: utils: Add cache flush libraryNick Hu1-0/+69
The current RISC-V CMO only defines how to flush a cache block. However, certain use cases, such as power management, may require flushing the entire cache. Therefore, a framework is being introduced to allow vendors to flush the entire cache using their own methods. Signed-off-by: Nick Hu <nick.hu@sifive.com> Reviewed-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251020-cache-upstream-v7-1-69a132447d8a@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-10-21lib: Allow custom CSRs in csr_read_num() and csr_write_num()Anup Patel1-0/+34
Some of the platforms use platform specific CSR access functions for configuring implementation specific CSRs (such as PMA registers). Extend the common csr_read_num() and csr_write_num() to allow custom CSRs so that platform specific CSR access functions are not needed. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Link: https://lore.kernel.org/r/20250930153216.89853-1-apatel@ventanamicro.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-09-16lib: utils/ipi: Convert IPI drivers as early driversAnup Patel1-26/+0
The fdt_ipi_init() is already called from generic_early_init() so let's convert IPI drivers as early drivers. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Samuel Holland <samuel.holland@sifive.com> Tested-by: Nick Hu <nick.hu@sifive.com> Link: https://lore.kernel.org/r/20250904052410.546818-4-apatel@ventanamicro.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-09-16include: sbi: Remove platform specific IPI initAnup Patel1-17/+0
The platform specfic IPI init is not need anymore because using IPI device rating multiple IPI devices can be registered in any order as part of the platform specific early init. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Samuel Holland <samuel.holland@sifive.com> Tested-by: Nick Hu <nick.hu@sifive.com> Link: https://lore.kernel.org/r/20250904052410.546818-3-apatel@ventanamicro.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-09-16lib: sbi: Introduce IPI device ratingAnup Patel1-2/+5
A platform can have multiple IPI devices (such as ACLINT MSWI, AIA IMSIC, etc). Currently, OpenSBI rely on platform calling the sbi_ipi_set_device() function in correct order and prefer the first avaiable IPI device which is fragile. Instead of the above, introduce IPI device rating and prefer the highest rated IPI device. This further allows extending the sbi_ipi_raw_clear() to clear all available IPI devices. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Tested-by: Nick Hu <nick.hu@sifive.com> Link: https://lore.kernel.org/r/20250904052410.546818-2-apatel@ventanamicro.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-09-01lib: sbi_list: Add a helper for reverse list iterationSamuel Holland1-0/+11
Some use cases require iterating through a list in both directions. Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Tested-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250617032306.1494528-2-samuel.holland@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-08-28dbtr: Add support for icount trigger typeJesse Taube1-0/+44
The linux kernel needs icount to implement hardware breakpoints. Signed-off-by: Jesse Taube <jesse@rivosinc.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250724183120.1822667-1-jesse@rivosinc.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-07-22include: sbi: Remove unused (LOG_)REGBYTESJessica Clarke1-7/+0
These are no longer used, so remove them. Signed-off-by: Jessica Clarke <jrtc27@jrtc27.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250709232932.37622-3-jrtc27@jrtc27.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-07-22include: sbi: Use array for struct sbi_trap_regs and GET/SET macrosJessica Clarke2-81/+92
Rather than hand-rolling scaled pointer arithmetic with casts and shifts, let the compiler do so by indexing an array of GPRs, taking advantage of the language's type system to scale based on whatever type the register happens to be. This makes it easier to support CHERI where the registers are capabilities, not plain integers, and so this pointer arithmetic would need to change (and currently REGBYTES is both the size of a register and the size of an integer word upstream). Signed-off-by: Jessica Clarke <jrtc27@jrtc27.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250709232932.37622-1-jrtc27@jrtc27.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-07-21include: sbi: Don't use #pragma when preprocessing device tree sourcesJessica Clarke1-0/+2
Since this persists in the preprocessed output (so that it can affect the subsequent compilation), it ends up in the input to dtc and is a syntax error, breaking the k210 build. Ideally we wouldn't add the -include flag to DTSCPPFLAGS in the first place as this header is wholly pointless there, but that's a more invasive build system change compared to just making this header safe to include there. Fixes: 86c01a73ff9d ("lib: sbi: Avoid GOT indirection for global symbol references") Signed-off-by: Jessica Clarke <jrtc27@jrtc27.com> Reviewed-by: Samuel Holland <samuel.holland@sifive.com> Tested-by: Xiang W <wxjstz@126.com> Reviewed-by: Xiang W <wxjstz@126.com> Link: https://lore.kernel.org/r/20250709232840.37551-1-jrtc27@jrtc27.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-07-20include: sbi: fix swap errors with newer gcc -Werror=sequence-pointBen Dooks1-3/+7
The BSWAPxx() macros are now throwing the following warnings with newer gcc versions. This is due to throwing an argument in that may be evaluated more than one (I think) and therefore things like the example below should be avoided. Fix by making a set of BSWAPxx() wrappers which specifically only evaluate 'x' once. In file included lib/sbi/sbi_mpxy.c:21: lib/sbi/sbi_mpxy.c: In function ‘sbi_mpxy_write_attrs’: ib/sbi/sbi_mpxy.c:632:63: error: operation on ‘mem_idx’ may be undefined [-Werror=sequence-point] 632 | attr_val = le32_to_cpu(mem_ptr[mem_idx++]); | ~~~~~~~^~ Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk> Reviewed-by: Rahul Pathak <rahul@summations.net> Reviewed-by: Xiang W <wxjstz@126.com> Link: https://lore.kernel.org/r/20250704122938.897832-1-ben.dooks@codethink.co.uk Signed-off-by: Anup Patel <anup@brainfault.org>
2025-07-20lib: sbi: Remove redundant call to sbi_hart_expected_trap_addr()Alvin Chang2-6/+2
The variable "sbi_hart_expected_trap" has already been extern variable. Therefore, the program can directly refer to it instead of calling sbi_hart_expected_trap_addr(). Signed-off-by: Alvin Chang <alvinga@andestech.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250703151957.2545958-2-alvinga@andestech.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-07-20lib: sbi_list: add a helper for safe list iterationYong-Xuan Wang1-0/+13
Some use cases require iterating safe against removal of list entry. Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250618025416.5331-1-yongxuan.wang@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-06-30include: Bump-up version to 1.7v1.7Anup Patel1-1/+1
Update the OpenSBI version to 1.7 as part of release preparation. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org>
2025-06-24lib: utils: Add Implementation ID and Version as RPMI MPXY attributesRahul Pathak2-1/+9
The latest frozen RPMI spec has added Implementation ID and Implementation Version as message protocol specific mpxy attributes. Add support for these. Signed-off-by: Rahul Pathak <rpathak@ventanamicro.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250618053854.2577299-1-rpathak@ventanamicro.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-06-17lib: sbi_platform: Add platform specific pmp_set() and pmp_disable()Chao-ying Fu1-0/+39
Allow platforms to implement platform specific PMP setup and PMP disable functions which are called before actual PMP CSRs are configured. Also, implement pmp_set() and pmp_disable() for MIPS P8700. Signed-off-by: Chao-ying Fu <cfu@mips.com> Signed-off-by: Anup Patel <apatel@ventanamicro.com> Link: https://lore.kernel.org/r/20250614172756.153902-1-apatel@ventanamicro.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-06-16lib: sbi: dbtr: Fix update_triggers to match SBIJesse Taube1-2/+1
OpenSBI implements sbi_dbtr_update_trig as `sbi_dbtr_update_trig(unsigned long trig_idx_base, unsigned long trig_idx_mask)` yet SBI v3.0-rc7 Chapter 19. Debug Triggers Extension [0] declares it as `sbi_debug_update_triggers(unsigned long trig_count)` Change update_triggers to match SBI. [0] https://github.com/riscv-non-isa/riscv-sbi-doc/tree/v3.0-rc7/src/ext-debug-triggers.adoc Fixes: 97f234f15c96 ("lib: sbi: Introduce the SBI debug triggers extension support") Signed-off-by: Jesse Taube <jesse@rivosinc.com> Reviewed-by: Himanshu Chauhan <hchauhan@ventanamicro.com> Tested-by: Charlie Jenkins <charlie@rivosinc.com> Reviewed-by: Charlie Jenkins <charlie@rivosinc.com> Link: https://lore.kernel.org/r/20250528154604.571815-1-jesse@rivosinc.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-06-16lib: sbi: dbtr: Fix shared memory layoutJesse Taube1-1/+1
The existing sbi_dbtr_shmem_entry has a size of 5 * XLEN with the final entry being idx. This is in contrast to the SBI v3.0-rc7 Chapter 19. Debug Triggers Extension [0] where idx and trig_state share the same offset (0) in shared memory, with a total size of 4 * XLEN for all the SBI calls. Replace struct with union to match memory layout described in SBI. [0] https://github.com/riscv-non-isa/riscv-sbi-doc/tree/v3.0-rc7/src/ext-debug-triggers.adoc Fixes: 97f234f15c96 ("lib: sbi: Introduce the SBI debug triggers extension support") Signed-off-by: Jesse Taube <jesse@rivosinc.com> Reviewed-by: Charlie Jenkins <charlie@rivosinc.com> Tested-by: Charlie Jenkins <charlie@rivosinc.com> Reviewed-by: Himanshu Chauhan <hchauhan@ventanamicro.com> Tested-by: Himanshu Chauhan <hchauhan@ventanamicro.com> Link: https://lore.kernel.org/r/20250604135225.842241-1-jesse@rivosinc.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-06-16lib: sbi: Revert entry_count before doing hsm stop in hsm wait loopAnup Patel1-0/+2
Using hsm stop in hsm wait loop causes secondary harts to be stuck forever in OpenSBI on RISC-V platforms where HSM hart hotplug is available and all harts come-up at the same time during system power-on. For example, lets say we have two harts A and B on a RISC-V platform with HSM hart hotplug which come-up at the same time during system power-on. The hart A enters OpenSBI before hart B hence it becomes the primary (or cold-boot) hart whereas hart B becomes the secondary (or warm-boot) hart. The hart A follows the OpenSBI cold-boot path and registers hsm device before hart B enters OpenSBI. The hart B eventually enters OpenSBI and follows the OpenSBI warm-boot path so it will increment it's own entry_count before entering hsm wait loop where it sees hsm device and stops itself. Later as part of the Linux boot-up sequence, hart A issues SBI HSM start call to bring-up hart B but OpenSBI sees entry_count != init_count for hart B in sbi_hsm_hart_start() hence hsm_device_hart_start() is not called for hart B resulting in hart B stuck forever in OpenSBI. To fix the above issue, revert entry_count before doing hsm stop in hsm wait loop. Fixes: d844deadec94 ("lib: sbi: Use hsm stop for hsm wait") Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Nick Hu <nick.hu@sifive.com> Link: https://lore.kernel.org/r/20250527124821.2113467-1-apatel@ventanamicro.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-05-20include: sbi: Change SBI spec version to 3.0Anup Patel1-1/+1
Now that SBI v3.0 specification is frozen, change runtime SBI version implemented by OpenSBI to v3.0. Also, mark extensions defined by the SBI v3.0 specification as non-experimental. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Clément Léger <cleger@rivosinc.com> Reviewed-by: Atish Patra <atishp@rivosinc.com> Link: https://lore.kernel.org/r/20250516122844.113423-1-apatel@ventanamicro.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-05-20lib: sbi: hart: Detect existence of cycle and instret CSRs for ZicntrYao Zi1-0/+10
Zicntr extension specifies three read-only CSRs, time, cycle and instret. It isn't sufficient to report Zicntr is fully supported with only time CSR detected. This patch introduces a bitmap to sbi_hart_features to record availability of these CSRs, which are detected using traps. Zicntr is reported as present if and only if three CSRs are all available on the HARTs. Sites originally depending on SBI_HART_EXT_ZICNTR for detecting existence of time CSR are switched to detect SBI_HART_CSR_TIME instead. Suggested-by: Anup Patel <anup@brainfault.org> Signed-off-by: Yao Zi <ziyao@disroot.org> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250516133352.36617-3-ziyao@disroot.org Signed-off-by: Anup Patel <anup@brainfault.org>
2025-05-20lib: utils: Fix fdt_mpxy_init() not returning error codeAlvin Chang1-2/+2
It seems that current implementation doesn't fail on fdt_mpxy_init(), because platforms might not have any MPXY devices. In fact, if there are no MPXY devices, fdt_driver_init_all() will return SBI_OK. More importantly, if there is any MPXY device which fails the initialization, OpenSBI must check the error code and stop the booting. Thus, this commit adds the return value for fdt_mpxy_init(). Signed-off-by: Alvin Chang <alvinga@andestech.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250430091007.3768180-1-alvinga@andestech.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-05-20lib: utils/mpxy: Remove p2a_db_index from RPMI system MSI attributesAnup Patel1-1/+0
The discovery of P2A doorbell system MSI index is now through RPMI shared memory DT node so remove p2a_db_index from RPMI system MSI attributes and access it as a mailbox channel attribute. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Link: https://lore.kernel.org/r/20250512083827.804151-5-apatel@ventanamicro.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-05-20lib: utils/mailbox: Parse P2A doorbell system MSI index from DTAnup Patel1-0/+1
The P2A doorbell system MSI index is expected to be discovered from device tree instead of RPMI system MSI service group attribute. This is based on ARC feedback before RPMI spec was frozen. Let's parse P2A doorbell system MSI index from device tree and also expose it as rpmi channel attribute to RPMI client drivers. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Link: https://lore.kernel.org/r/20250512083827.804151-3-apatel@ventanamicro.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-05-20lib: Emulate AMO instructions when Zaamo is not availableChao-ying Fu3-14/+41
The AMO instructions are very critical for Linux so allow low-end RISC-V implementations without Zaamo to boot Linux by emulating AMO instructions using Zalrsc when OpenSBI is compiled without Zaamo. Signed-off-by: Chao-ying Fu <cfu@mips.com> Signed-off-by: Anup Patel <apatel@ventanamicro.com> Link: https://lore.kernel.org/r/20250519121207.976949-1-apatel@ventanamicro.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-04-30lib: sbi_hart: add Ssstateen extensionRadim Krčmář1-1/+3
We already detect Smstateen, but Ssstateen exists as well and it doesn't have the M-state CSRs. Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Radim Krčmář <rkrcmar@ventanamicro.com> Link: https://lore.kernel.org/r/20250429142549.3673976-9-rkrcmar@ventanamicro.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-04-30lib: sbi: add 64 bit csr macrosRadim Krčmář1-0/+20
Most CSRs are XLEN bits wide, but some are 64 bit, so rv32 needs two accesses, plaguing the code with ifdefs. Add new helpers that split 64 bit operation into two operations on rv32. The helpers don't use "csr + 0x10", but append "H" at the end of the csr name to get a compile-time error when accessing a non 64 bit register. This has the downside that you have to use the name when accessing them. e.g. csr_read64(0x1234) or csr_read64(CSR_SATP) won't compile and the error messages you get for these bugs are not straightforward. Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Radim Krčmář <rkrcmar@ventanamicro.com> Link: https://lore.kernel.org/r/20250429142549.3673976-3-rkrcmar@ventanamicro.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-04-24lib: sbi: Set the scratch allocation to alignment to cacheline sizeRaj Vishwanathan2-0/+7
Set the scratch allocation alignment to cacheline size specified by riscv,cbom-block-size in the DTS file to avoid two atomic variables from the same cache line causing livelock on some platforms. If the cacheline is not specified, we set it a default value. Signed-off-by: Raj Vishwanathan <Raj.Vishwanathan@gmail.com> Reviewed-by: Anup Patel <anup@brainfault.org> Reviewed-by: Samuel Holland <samuel.holland@sifive.com> Link: https://lore.kernel.org/r/20250423225045.267983-1-Raj.Vishwanathan@gmail.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-04-23lib: sbi_platform: Remove the vendor_ext_check hookSamuel Holland1-6/+1
Now that the generic platform only sets .vendor_ext_provider if the function is really implemented, there is no need for a separate hook to check if a vendor extension is implemented. Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250325234342.711447-11-samuel.holland@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-04-23lib: utils/fdt: Remove fdt_match_node()Samuel Holland1-3/+0
This function has been obsoleted by the fdt_driver library and is no longer used. Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250325234342.711447-10-samuel.holland@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-04-15lib: sbi: Simplify structure member offset checkingXiang W4-130/+39
Add a macro assert_member_offset() to perform structure member offset checking. Signed-off-by: Xiang W <wxjstz@126.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250319123919.505443-1-wxjstz@126.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-04-14sbi: Introduce sbi_hartmask_weightAndrew Jones3-7/+39
Provide a function to count the number of set bits in a hartmask, which builds on a new function for the same that operates on a bitmask. While at it, improve the performance of sbi_popcount() which is used in the implementation. Signed-off-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250314163021.154530-5-ajones@ventanamicro.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-04-13lib: sbi: Enable Control Transfer Records (CTR) Ext using xstateen.Rajnesh Kanwal2-0/+17
The Control Transfer Records (CTR) extension provides a method to record a limited branch history in register-accessible internal chip storage. This extension is similar to Arch LBR in x86 and BRBE in ARM. The Extension has been stable and the latest release can be found here https://github.com/riscv/riscv-control-transfer-records/release Signed-off-by: Rajnesh Kanwal <rkanwal@rivosinc.com> Reviewed-by: Atish Patra <atishp@rivosinc.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250307124451.122828-1-rkanwal@rivosinc.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-04-13lib: sbi_trap: Add support for vectored interruptsSamuel Holland1-0/+2
When redirecting an exception to S-mode, transform the (v)stvec CSR value as described in the privileged spec to derive the S-mode PC. Since OpenSBI never redirects interrupts, only synchronous exceptions, the only action needed is to mask out the (v)stvec.MODE field. Reported-by: Jan Reinhard <jan.reinhard@sysgo.com> Closes: https://github.com/riscv-software-src/opensbi/issues/391 Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Reviwed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250305014729.3143535-1-samuel.holland@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-03-27lib: utils/serial: Add PXA UARTs supportJunhui Liu1-1/+3
The PXA variant of the uart8250 adds the UART Unit Enable bit (UUE) that needs to be set to enable the XScale PXA UART. And it is required for some RISC-V SoCs like the Spacemit K1 that implement the PXA UART. This introduces the "intel,xscale-uart" compatible to handle setting the UUE bit. Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250327-pxa-uart-support-v2-1-c4400c1fcd0b@pigmoral.tech Signed-off-by: Anup Patel <anup@brainfault.org>
2025-03-27lib: sbi: sse: Add support for SSTATUS.SDTClément Léger2-1/+3
Similarly to what is done for SPELP, handle SSTATUS.SDT upon event injection. In order to mimick an interrupt, set SDT to 1 for injection and save its previous value in interrupted_flags[5:5]. Restore it upon completion. Signed-off-by: Clément Léger <cleger@rivosinc.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
2025-03-27lib: sbi: sse: Add support for SSTATUS.SPELPClément Léger1-0/+1
As raised during the ARC review, SPELP was not handled during the event injection process. Save it as part of the interrupted flags, clear it before injecting the event and restore it after completion. Signed-off-by: Clément Léger <cleger@rivosinc.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
2025-03-27lib: sbi: sse: Rename STATUS* interrupted flags to SSTATUS*Clément Léger1-2/+2
As raised by Andrew on the kvm-unit-test review, this flags are meant to hold SSTATUS bits in the specification. Rename them to match that. Signed-off-by: Clément Léger <cleger@rivosinc.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
2025-03-27lib: sbi: sse: Update SSE event idsClément Léger1-9/+35
The latest specification added new high priority RAS events and renamed the PMU to PMU_OVERFLOW. Signed-off-by: Clément Léger <cleger@rivosinc.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
2025-03-24lib: sbi: Use sbi_hart_count() and sbi_for_each_hartindex()Samuel Holland2-4/+1
Simplify the code and improve consistency by using the new macros where possible. sbi_hart_count() obsoletes sbi_scratch_last_hartindex(). Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2025-03-24lib: sbi_scratch: Add sbi_hart_count() and for_each_hartindex()Samuel Holland1-5/+11
There is currently no helper for iterating through the harts in a system, and code must choose between sbi_scratch_last_hartindex() and sbi_platform_hart_count() for the loop condition. sbi_scratch_last_hartindex() has unusual semantics, leading to the likelihood of off-by-one errors, and sbi_platform_hart_count() is provided by the platform and so may not be properly bounded. Add a new helper which definitively reports the number of harts managed by this OpenSBI instance, i.e. the number of valid hart indexes, and a convenient iterator macro. Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2025-03-24lib: sbi_scratch: Optimize hartid and scratch lookupSamuel Holland1-3/+3
The compiler generates much better code for sbi_hartindex_to_hartid() and sbi_hartindex_to_scratch() when using a constant for the bounds check. This works out nicely because the underlying arrays are already a constant size, so the only change needed is to fill the remainder of each array with the appropriate default/out-of-bounds value. The ellipsis in the designated initializer is a GCC extension (also supported by Clang), but avoids runtime initialization of the array. Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2025-03-24lib: sbi_scratch: Apply bounds check to platform hart_countSamuel Holland1-8/+3
The internal limit on the number of harts is SBI_HARTMASK_MAX_BITS, as this value determines the size of various bitmaps and arrays (including hartindex_to_hartid_table and hartindex_to_scratch_table). Clamp the value provided by the platform, and drop the extra array element. Update the documentation to indicate that hart_index2id must be sized based on hart_count, and that hart indexes must be contiguous. As of commit 5e90e54a1a53 ("lib: utils:Check that hartid is valid"), there is no restriction on the valid hart ID values. Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2025-03-24lib: sbi: Avoid GOT indirection for global symbol referencesSamuel Holland1-0/+16
OpenSBI is compiled with -fPIE, which generally implies dynamic linking. This causes the compiler to generate GOT references for global symbols in order to support runtime symbol interposition. However, OpenSBI does not actually perform dynamic linking, so the GOT indirection just adds unnecessary overhead. The GOT references can be avoided by declaring global symbols with hidden visibility, thus making them local to this dynamic object and non-interposable. GCC/Clang's -fvisibility parameter is insufficient for this purpose when referencing objects from other translation units; either __attribute__((visibility(...)) or the pragma is required. Use the pragma since it is easier to apply to every symbol. Additionally clean up the one GOT reference from inline assembly. With this change, a firmware linked with LLD does not contain either a GOT or a PLT, and a firmware linked with BFD ld contains only a GOT with a single (unreferenced, legacy) _GLOBAL_OFFSET_TABLE_ entry. Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2025-03-23lib: add tests for sbi_ecall functionalityAkshay Behl1-0/+2
This patch adds unit tests for verifying the sbi_ecall version, impid handling, and extension registration functions. The tests ensure that the extension registration and unregistration work as expected. Signed-off-by: Akshay Behl <akshaybehl231@gmail.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2025-02-19include: sbi: Add SBI_ERR_DENIED_LOCKEDClément Léger2-1/+3
Add SBI_ERR_DENIED_LOCKED and set it as the SBI_LAST_ERR which was wrongly set to SBI_ERR_BAD_RANGE. Signed-off-by: Clément Léger <cleger@rivosinc.com> Reviewed-by: Anup Patel <anup@brainfault.org>
generated by cgit v1.2.3 (git 2.39.1) at 2026-05-16 13:56:24 +0000