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| author | Clément Léger <cleger@rivosinc.com> | 2025-05-19 10:39:49 +0200 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2025-06-15 18:44:51 +0530 |
| commit | f30a54f3b3a091c225a00476f4039bf399badd1f (patch) | |
| tree | a0dfdba18f646debd52113c30f1e5b7b18acee71 | |
| parent | b31a0a24279d46ae4981e1691fe56e245b6d39a0 (diff) | |
| download | opensbi-f30a54f3b3a091c225a00476f4039bf399badd1f.zip opensbi-f30a54f3b3a091c225a00476f4039bf399badd1f.tar.gz opensbi-f30a54f3b3a091c225a00476f4039bf399badd1f.tar.bz2 | |
lib: sbi: pmu: Remove MIP clearing from pmu_sse_enable()
Clearing MIP at that point means that we can probably lose a pending
interrupt. This should not happen, remove MIP clearing from there.
Signed-off-by: Clément Léger <cleger@rivosinc.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
Reviewed-by: Samuel Holland <samuel.holland@sifive.com>
Link: https://lore.kernel.org/r/20250519083950.739044-3-cleger@rivosinc.com
Signed-off-by: Anup Patel <anup@brainfault.org>
| -rw-r--r-- | lib/sbi/sbi_pmu.c | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/lib/sbi/sbi_pmu.c b/lib/sbi/sbi_pmu.c index 9b779c5..07a5c54 100644 --- a/lib/sbi/sbi_pmu.c +++ b/lib/sbi/sbi_pmu.c @@ -1104,7 +1104,6 @@ static void pmu_sse_enable(uint32_t event_id) { unsigned long irq_mask = sbi_pmu_irq_mask(); - csr_clear(CSR_MIP, irq_mask); csr_set(CSR_MIE, irq_mask); } |