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| author | Radim Krčmář <rkrcmar@ventanamicro.com> | 2025-04-29 16:25:50 +0200 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2025-04-30 10:14:26 +0530 |
| commit | 316daaf1c299c29ac46e52145f65521f48ec63b5 (patch) | |
| tree | 7d34754a75edcd9cfa2b0a19c85940ae7debde8d /lib/utils/cppc | |
| parent | 937118ca6520c7d61af5d792917610a234bb6c3a (diff) | |
| download | opensbi-316daaf1c299c29ac46e52145f65521f48ec63b5.zip opensbi-316daaf1c299c29ac46e52145f65521f48ec63b5.tar.gz opensbi-316daaf1c299c29ac46e52145f65521f48ec63b5.tar.bz2 | |
lib: sbi_hart: properly reset Ssstateen
sstateen* and hstateen* CSRs must be zeroed by M-mode if the mstateen*
registers are missing, to avoid security issues.
Reviewed-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Radim Krčmář <rkrcmar@ventanamicro.com>
Link: https://lore.kernel.org/r/20250429142549.3673976-10-rkrcmar@ventanamicro.com
Signed-off-by: Anup Patel <anup@brainfault.org>
Diffstat (limited to 'lib/utils/cppc')
0 files changed, 0 insertions, 0 deletions