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path: root/riscv/processor.h
AgeCommit message (Expand)AuthorFilesLines
2013-10-18refactor disassembler, and add hwacha disassemblerYunsup Lee1-4/+7
2013-08-13Implement RoCC and add a dummy RoCCAndrew Waterman1-12/+25
2013-08-11Instructions are no longer member functionsAndrew Waterman1-32/+37
2013-07-26Remove more vector stuffAndrew Waterman1-21/+0
2013-07-26Rip out RVC for nowAndrew Waterman1-14/+0
2013-07-26Generate instruction decoder dynamicallyAndrew Waterman1-7/+26
2013-03-29add load-reserved/store-conditional instructionsAndrew Waterman1-5/+0
2013-03-25add BSD licenseAndrew Waterman1-0/+2
2013-03-25expose pending interrupts in status registerAndrew Waterman1-1/+1
2013-02-13add I$/D$/L2$ simulatorsAndrew Waterman1-0/+1
2013-01-25change htif to link against libfesvrAndrew Waterman1-1/+1
2012-08-30new tohost/fromhost semanticsAndrew Waterman1-0/+1
2012-07-22correct HTIF reset behaviorAndrew Waterman1-3/+2
2012-05-09per-core tohost/fromhost registersAndrew Waterman1-3/+6
2012-03-24new supervisor modeAndrew Waterman1-4/+5
2012-03-19abstract regfile behind objectAndrew Waterman1-2/+2
2012-01-22disentangle decode.h from other headersAndrew Waterman1-0/+15
2011-11-11Changed supervisor modeAndrew Waterman1-2/+3
2011-06-19temporary undoing of renamingAndrew Waterman1-0/+89
2011-06-12[sim] renamed to riscv-isa-runAndrew Waterman1-97/+0
2011-06-12[xcc] minor performance tweaksAndrew Waterman1-1/+2
2011-06-11[xcc] fixed simulator build timeAndrew Waterman1-9/+1
2011-06-11[xcc] cleaned up mmu codeAndrew Waterman1-2/+2
2011-06-10[sim, opcodes] made sim more decoupled from opcodesAndrew Waterman1-2/+12
2011-05-29[sim,opcodes] improved sim build and run performanceAndrew Waterman1-0/+3
2011-05-28[fesvr,xcc,sim] fixed multicore sim for akarosAndrew Waterman1-0/+4
2011-05-23[sim,xcc] add rdcycle/rdtime/rdinstretAndrew Waterman1-1/+1
2011-05-19[sim] vlen calc reflects the hardwareYunsup Lee1-5/+5
2011-05-18[opcodes,pk,sim] add more vector traps (for #banks, illegal instructions)Yunsup Lee1-0/+2
2011-04-30[sim] hacked in a dcache simulatorAndrew Waterman1-2/+5
2011-04-15[sim] added icache simulator (disabled by default)Andrew Waterman1-1/+6
2011-04-09[sim] add vt stuffYunsup Lee1-1/+17
2011-02-04[sim,pk] added interrupt-pending field to cause regAndrew Waterman1-1/+0
2011-01-18[opcodes, sim, xcc] made *w insns illegal in RV32Andrew Waterman1-4/+4
2010-10-26[pk,sim,xcc] get rid of at register, introduce tp registerYunsup Lee1-1/+0
2010-10-05[xcc,sim] eliminated vectored trapsAndrew Waterman1-1/+2
2010-09-09Merge branch 'master' of /project/eecs/parlab/git/projects/riscvAndrew Waterman1-0/+2
2010-09-09[pk, sim] added interrupt support to sim; added timer interruptAndrew Waterman1-0/+3
2010-09-08[sim] add while to interactive_untilYunsup Lee1-0/+2
2010-09-07[sim] yet another fix stdint.h __STDC_LIMIT_MACROS problemYunsup Lee1-1/+1
2010-09-06[sim, xcc] added PCRs to replace k0 and k1Andrew Waterman1-0/+2
2010-09-06[sim, xcc] bthread threading model exposed; insn encoding cleaned upAndrew Waterman1-0/+7
2010-08-24[sim] privileged mode support for 32-bit operationAndrew Waterman1-1/+1
2010-08-09[xcc,sim] implement FP using softfloatAndrew Waterman1-0/+2
2010-08-04[xcc,pk,sim] Added first part of FP supportAndrew Waterman1-0/+1
2010-07-21[pk,sim] first cut of appserver communication linkAndrew Waterman1-1/+6
2010-07-18Reorganized directory structureAndrew Waterman1-0/+40
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