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AgeCommit message (Expand)AuthorFilesLines
2013-11-29Remove debug printf in vsetprecconfprecQuan Nguyen1-1/+0
2013-11-29Add vsetprec instruction prototypeQuan Nguyen5-0/+17
2013-11-24Merge branch 'master' of github.com:ucb-bar/riscv-isa-sim into HEADQuan Nguyen7-4/+9
2013-11-21fix slli/slliw encoding bugYunsup Lee2-4/+4
2013-11-05add accelerator disabled causeYunsup Lee1-0/+1
2013-11-05correctly trap when SR_EA is disabledYunsup Lee4-0/+4
2013-11-04Fix declaration of half-precision instructionsAlbert Ou2-0/+2
2013-11-04Re-add Hwacha header fileAlbert Ou1-0/+1
2013-11-04Implement "half-baked" half-precision instruction subset for HwachaAlbert Ou39-2/+336
2013-11-04Merge branch 'master' of github.com:ucb-bar/riscv-isa-sim into confprecAlbert Ou30-180/+463
2013-10-28include stdexceptYunsup Lee1-0/+1
2013-10-28Pass target machine's return code back to OSAndrew Waterman3-3/+4
2013-10-27Add missing fcvt opcodes through riscv-opcodesQuan Nguyen1-37/+4
2013-10-21clarify vxcptsave/vxctkill semanticsYunsup Lee3-3/+7
2013-10-18implement vxcptsave/vxcptrestoreYunsup Lee4-3/+82
2013-10-18clean up SR_EA, the enable accelerator bit in status regYunsup Lee2-5/+4
2013-10-18more hwacha supervisor stuffYunsup Lee6-17/+21
2013-10-18refactor disassembler, and add hwacha disassemblerYunsup Lee17-144/+347
2013-10-18can't execute frsr/fssr on utYunsup Lee3-4/+0
2013-10-18or into control thread's fp exceptionsYunsup Lee1-4/+0
2013-10-17Add empty opcode header files for half-precisionQuan Nguyen34-4/+37
2013-10-17catch trap_illegal_instruction in hwachaYunsup Lee1-0/+4
2013-10-17add hwacha exception supportYunsup Lee16-38/+213
2013-10-17fix custom-1 rocc encodingYunsup Lee1-1/+1
2013-10-16fix maxvl calc logicYunsup Lee1-1/+5
2013-10-16use reset virtual methodYunsup Lee3-4/+5
2013-10-16use uint32_t for vlYunsup Lee1-1/+1
2013-10-16fix missing null check when there's no extensionYunsup Lee1-1/+2
2013-10-16revamp hwacha; now runs in physical modeYunsup Lee252-267/+718
2013-10-15Propogate the reset call to the extensions as well. Add reset function to ext...Stephen Twigg3-1/+8
2013-10-15Fix bug where xs2 was not being properly respected.Stephen Twigg1-1/+1
2013-10-10commit configure script; new configure option --enable-commitlogYunsup Lee2-0/+18
2013-09-27Added commit logging (--enable-commitlog). Also fixed disasm bug.Christopher Celio4-6/+54
2013-09-27Use WRITE_RD/WRITE_FRD macros to write registersAndrew Waterman141-185/+167
2013-09-26Bye, CBAndrew Waterman1-34/+0
2013-09-23fixes compile bug for not being able to find std::logic_errorScott Beamer1-0/+1
2013-09-23Fix Scott's deadlockAndrew Waterman3-7/+11
2013-09-22Adjust rocc_inst_t to properly extract fields due to the new ISA encoding.Stephen Twigg1-3/+3
2013-09-21Update ISA encoding and AUIPC semanticsAndrew Waterman3-168/+170
2013-09-15Add helper disassembly programAndrew Waterman2-0/+42
2013-09-15ISA changesAndrew Waterman1-2/+2
2013-09-11Add AMOXORAndrew Waterman3-16/+25
2013-09-11Implement zany immediatesAndrew Waterman39-459/+233
2013-09-10Don't tick HTIF as oftenAndrew Waterman1-4/+4
2013-09-10Add rd field to JAL; drop JAndrew Waterman6-42/+33
2013-08-18Renumber PCRsAndrew Waterman2-23/+20
2013-08-13Add test program for dummy roccAndrew Waterman1-0/+29
2013-08-13Implement RoCC and add a dummy RoCCAndrew Waterman11-40/+249
2013-08-11Instructions are no longer member functionsAndrew Waterman65-309/+337
2013-08-08Ignore JALR's effective address LSBAndrew Waterman1-1/+1
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