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2023-09-12pldm: Export logging featureChristophe Lombard1-0/+1
To retrieve specific log traces from the external library: libmctp, we need to export the logging api. Signed-off-by: Christophe Lombard <clombard@linux.ibm.com> Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
2022-06-13core: detect LPAR-per-core mode and report in dtNicholas Piggin1-0/+2
Some firmware configurations boot in LPAR-per-core mode, which is not compatible with KVM on POWER9 and later machines. Detect which LPAR mode the boot core is in (all others will be set the same way), and if booted in LPAR-per-core mode then print a warning and add a device-tree entry that the OS can test for. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
2022-01-03hw/slw: split P8 specific code into its own fileNicholas Piggin1-12/+0
POWER8 support is large and significantly different than P9/10 code. This change prepares to make P8 support configurable. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> [ clg: Removed commented headers in slw.c ] Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-01-03hwprobe: convert PHB, NPU, PAU subsystems to hwprobeStewart Smith1-5/+0
Reviewed-by: Dan Horák <dan@danny.cz> [npiggin: split out from initial hwprobe pach] Signed-off-by: Stewart Smith <stewart@flamingspork.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-01-03Introduce hwprobe facility to avoid hard-coding probe functionsStewart Smith1-1/+38
hwprobe is a little system to have different hardware probing modules run in the dependency order they choose rather than hard coding that order in core/init.c. Reviewed-by: Dan Horák <dan@danny.cz> Signed-off-by: Stewart Smith <stewart@flamingspork.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-10-19pau: introduce supportChristophe Lombard1-0/+1
OpenCapi for P10 is included in the P10 chip. This requires OCAPI capable PHYs, Datalink Layer Logic and Transaction Layer Logic to be included. The PHYs are the physical connection to the OCAPI interconnect. The Datalink Layer provides link training. The Transaction Layer executes the cache coherent and data movement commands on the P10 chip. The PAU provides the Transaction Layer functionality for the OCAPI link(s) on the P10 chip. The P10 PAU supports two OCAPI links. Six accelerator units PAUs are instantiated on the P10 chip for a total of twelve OCAPI links. This patch adds PAU opencapi structure for supporting OpenCapi5. hw/pau.c file contains main of PAU management functions. Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-10-19Remove support for POWER8 DD1Nicholas Piggin1-5/+0
This significantly simplifies the SLW code. HILE is now always supported. Reviewed-by: Stewart Smith <stewart@flamingspork.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-10-13HBRT: fix clobbered r16 when host services handlers are calledNicholas Piggin1-0/+5
Skiboot is using r16 as a fixed register containing this CPU pointer, but we can be called back into from hostboot via the host services interface, where r16 may have been set by hostboot. Switch this back to skiboot's CPU pointer before running host services handlers, and then restore it to the hostboot value before returning. Fixes: 11ce9612b3aa ("move the __this_cpu register to r16, reserve r13-r15") Reported-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com> Tested-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-09-09npu3: Remove GPU support on SwiftFrederic Barrat1-1/+0
npu3 was only used on the Swift platform to add support for GPUs (nvlink). The Swift platform has never left the lab and support for GPUs on it is pretty much dead. So let's remove it. The patch removes all related code. Device tree entries are no longer created and in the very unlikely case that someone is still trying to boot it, the linux nvlink discovery code should be quiet. Tested by booting on Swift with no GPU. Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Reviewed-by: Reza Arbab <arbab@linux.ibm.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-08-06Initial POWER10 enablementNicholas Piggin1-0/+1
Co-authored-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Co-authored-by: Vaidyanathan Srinivasan <svaidy@linux.ibm.com> Signed-off-by: Vaidyanathan Srinivasan <svaidy@linux.ibm.com> Co-authored-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Michael Neuling <mikey@neuling.org> Co-authored-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Co-authored-by: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com> Signed-off-by: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com> Co-authored-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2020-12-15hw/ocmb: Clear top bit from offset before searching addr rangeVasant Hegde1-0/+6
Looks like HBRT sets top bit in pcbaddress before making OCMB SCOM request. We have to clear that bit so that we can find proper address range for SCOM operation. Sample failure: [ 2578.156011925,3] OCMB: no matching address range! [ 2578.156044481,3] scom_read: to 80000028 off: 8006430d4008c000 rc = -26 Also move HRMOR_BIT macro to common include file (hdata/spira.h -> skiboot.h). Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2020-10-01core/flash.c: add SECBOOT read and write supportClaudio Carvalho1-0/+3
In secure boot enabled systems, the petitboot linux kernel verifies the OS kernel against x509 certificates that are wrapped in secure variables controlled by OPAL. These secure variables are stored in the PNOR SECBOOT partition, as well as the updates submitted for them using userspace tools. This patch adds read and write support to the PNOR SECBOOT partition in a similar fashion to that of NVRAM, so that OPAL can handle the secure variables. Signed-off-by: Claudio Carvalho <cclaudio@linux.ibm.com> Signed-off-by: Eric Richter <erichte@linux.ibm.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2020-03-12Re-license IBM written files as Apache 2.0 OR GPLv2+Stewart Smith1-1/+1
SPDX makes it a simpler diff. I have audited the commit history of each file to ensure that they are exclusively authored by IBM and thus we have the right to relicense. The motivation behind this is twofold: 1) We want to enable experiments with coreboot, which is GPLv2 licensed 2) An upcoming firmware component wants to incorporate code from skiboot and code from the Linux kernel, which is GPLv2 licensed. I have gone through the IBM internal way of gaining approval for this. The following files are not exclusively authored by IBM, so are *not* included in this update (I will be seeking approval from contributors): core/direct-controls.c core/flash.c core/pcie-slot.c external/common/arch_flash_unknown.c external/common/rules.mk external/gard/Makefile external/gard/rules.mk external/opal-prd/Makefile external/pflash/Makefile external/xscom-utils/Makefile hdata/vpd.c hw/dts.c hw/ipmi/ipmi-watchdog.c hw/phb4.c include/cpu.h include/phb4.h include/platform.h libflash/libffs.c libstb/mbedtls/sha512.c libstb/mbedtls/sha512.h platforms/astbmc/barreleye.c platforms/astbmc/garrison.c platforms/astbmc/mihawk.c platforms/astbmc/nicole.c platforms/astbmc/p8dnu.c platforms/astbmc/p8dtu.c platforms/astbmc/p9dsu.c platforms/astbmc/vesnin.c platforms/rhesus/ec/config.h platforms/rhesus/ec/gpio.h platforms/rhesus/gpio.c platforms/rhesus/rhesus.c platforms/astbmc/talos.c platforms/astbmc/romulus.c Signed-off-by: Stewart Smith <stewart@linux.ibm.com> [oliver: fixed up the drift] Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-12-16fix simple sparse warningsNicholas Piggin1-1/+1
Should be no real code change, these mostly update type declarations that sparse complains about. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-11-04xive/p9: minor cleanup of the interfaceCédric Le Goater1-1/+0
The XIVE driver exposes an API to the core OPAL layer and to other OPAL drivers. This is a minor cleanup preparing ground for future XIVE logic. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-10-14core/init: Don't checksum MPIPL data areasOliver O'Halloran1-0/+1
Right now the romem checksum runs from _start until the start of our data area. This spans the area used for the MPIPL data structures since they're included in the SPIRA-H data area. Reviewed-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-10-03core/util: trap based assertionsNicholas Piggin1-0/+1
Using traps for assertions like Linux does gives a few advantages: - The asm code leading to the failure condition is nicer. - The interrupt gives a clean snapshot of machine state to dump. The difficulty with using traps for this in OPAL is that the runtime component will not deal well with the OS taking the 0x700 interrupt caused by a trap in OPAL. The long term goal is to improve the ability of the OS to inspect and debug OPAL at runtime. For now though, the traps are patched out before passing control to the OS, and the assert falls through to in-line failure handling. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> [oliver: commit prefix, added and renamed the FWTS label, fix tests] Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-08-16pci: Use a macro for accessing PCI BDF Function NumberJordan Niethe1-0/+1
Currently when the Function Number bits of a BDF are needed the bit operations to get it are free coded. There are many places where the Function Number is used, so make a macro to use instead of free coding it everytime. Signed-off-by: Jordan Niethe <jniethe5@gmail.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-08-16pci: Use a macro for accessing PCI BDF Device NumberJordan Niethe1-0/+1
Currently when the Device Number bits of a BDF are needed the bit operations to get it are free coded. There are many places where the Device Number is used, so make a macro to use instead of free coding it everytime. Signed-off-by: Jordan Niethe <jniethe5@gmail.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-08-16pci: Use a macro for accessing PCI BDF Bus NumberJordan Niethe1-0/+3
Currently when the Bus Number bits of a BDF are needed the bit operations to get it are free coded. There are many places where the Bus Number is used, so make a macro to use instead of free coding it everytime. Signed-off-by: Jordan Niethe <jniethe5@gmail.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-08-15HIOMAP: Reset bmc mbox in MPIPL pathVasant Hegde1-0/+1
During boot SBE and early hostboot does not use HIOMAP protocol to get image from PNOR. Instead it expects PNOR TOC and Hostboot Boot Loader to be available at particular address in LPC bus. mbox daemon in BMC side takes care of this during normal boot. Once boot is complete mbox daemon switches to normal mode. During normal reboot, BMC side mbox daemon gets notification and takes care of loading PNOR TOC and HBBL to LPC bus again. In MPIPL path, OPAL calls SBE S0 interrupt to initiate MPIPL. BMC will not be aware of this. But SBE expects PNOR TOC and HBBL to be available in LPC bus at predefined address. Hence call HIOMAP Reset from OPAL in assert path. This needs working LPC and IPMI driver in OPAL. If we have issue in these drivers then we may not be able to reset BMC MBOX properly. Hence MPIPL may fail. We have to live with this until we find a way to intiate BMC on MPIPL. CC: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> [oliver: rebased] Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-07-26hw: Introduce npu3Reza Arbab1-0/+1
POWER9P systems have been upgraded with NVLink 3.0 interconnects. The underlying hardware is fundamentally different--each POWER9 chip has (1 NPU) * (3 stacks) * (2 bricks) = (6 links) Where in each POWER9P chip, there are (3 NPUs) * (4 bricks) = (12 links) This flatter hierarchy simplifies the firmware implementation a bit, but also prevents sharing much common code with npu2. As in previous versions, initialize the hardware and expose each link to the OS as a virtual PCIe device. This initial support covers NVLink devices only, with OpenCAPI to follow. Signed-off-by: Reza Arbab <arbab@linux.ibm.com> Reviewed-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-07-26SPDX-ify all skiboot codeStewart Smith1-15/+2
Use Software Package Data Exchange (SPDX) to indicate license for each file that is unique to skiboot. At the same time, ensure the (C) who and years are correct. See https://spdx.org/ Signed-off-by: Stewart Smith <stewart@linux.ibm.com> [oliver: Added a few missing files] Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-06-04Remove POWER7 and POWER7+ supportStewart Smith1-2/+0
It's been a good long while since either OPAL POWER7 user touched a machine, and even longer since they'd have been okay using an old version rather than tracking master. There's also been no testing of OPAL on POWER7 systems for an awfully long time, so it's pretty safe to assume that it's very much bitrotted. It also saves a whole 14kb of xz compressed payload space. Signed-off-by: Stewart Smith <stewart@linux.ibm.com> Enthusiasticly-Acked-by: Oliver O'Halloran <oohall@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
2019-06-03prd: Implement generic FSP - HBRT interfaceVasant Hegde1-0/+1
This patch implements generic interface to pass data from FSP to HBRT during runtime (FSP -> OPAL -> opal-prd -> HBRT). OPAL gets notification from FSP for new HBRT messages. We will convert MBOX message to firmware_notify format and send it to HBRT. Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
2019-06-03prd: Implement generic HBRT - FSP interfaceVasant Hegde1-0/+1
This patch implements generic interface to pass data from HBRT to FSP during runtime (HBRT -> opal-prd -> kernel -> OPAL -> FSP). HBRT sends data via firmware_request interface. We have to convert that to MBOX format and send it to FSP. OPAL uses TCE mapped memory to send data. FSP will reuse same memory for response. Once processing is complete FSP sends response to OPAL. Finally OPAL calls HBRT with firmware_response message. Also introduces new opal_msg type (OPAL_MSG_PRD2) to pass bigger prd message to kernel. - if (prd_msg > OPAL_MSG_FIXED_PARAMS_SIZE) use OPAL_MSG_PRD2 Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
2019-02-25flash: Add support for async decompressionSantosh Sivaraj1-0/+34
Implement a standard API for decompressing images using the existing method found in the IMC code. This patch also standardizes error codes and does the decompression asynchronously. The IMC decompress() function is refactored to decompress blobs/images as a separate CPU job. 'xz_decompress_start()' starts the decompression in a newly created CPU job; while 'wait_xz_decompress()' waits for the job to complete. The IMC code will be first user for the new APIs; whose implementation is provided as reference in the next patch. Signed-off-by: Santosh Sivaraj <santosh@fossix.org> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
2019-02-13core/exceptions: implement support for MCE interrupts in powersaveNicholas Piggin1-2/+3
The ISA specifies that MCE interrupts in power saving modes will enter at 0x200 with powersave bits in SRR1 set. This is not currently supported properly, the MCE will just happen like a normal interrupt, but GPRs could be lost, which would lead to crashes (e.g., r1, r2, r13 etc). So check the power save bits similarly to the sreset vector, and handle this properly. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
2019-02-13core/exceptions: allow recoverable sreset exceptionsNicholas Piggin1-2/+2
This requires implementing the MSR[RI] bit. Then just allow all non-fatal sreset exceptions to recover. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
2019-02-13core/exceptions: implement an exception handler for non-powersave sresetsNicholas Piggin1-0/+5
Detect non-powersave sresets and send them to the normal exception handler which prints registers and stack. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
2019-02-13core/fast-reboot: fast reboot specific sreset patchNicholas Piggin1-0/+3
Provide an sreset handler specifically for fast reboots, which allows FIXUP_ENDIAN to be removed from the normal sreset handler in the next patch. The save_1 == 0 condition is no longer required to signal a fast reboot. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
2019-02-12core/init: rename setup_reset_vectorNicholas Piggin1-1/+1
Use the word copy, to match copy_exception_vectors. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
2018-09-20skiboot.lds.S: move read-write data after the end of symbol mapNicholas Piggin1-0/+7
This also tidies up linker script symbol declarations and adds _rodata_mem symbol for the next change to use. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
2018-09-18Add fast-reboot property to /ibm,opal DT nodeStewart Smith1-0/+1
this means that if it's permanently disabled on boot, the test suite can pick that up and not try a fast reboot test. Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
2018-09-17hw/npu2: Common NPU2 init routine between NVLink and OpenCAPIAndrew Donnellan1-1/+0
Replace probe_npu2() and probe_npu2_opencapi() with a new shared probe_npu2(). Refactor some of the common NPU setup code into shared code. No functional change. This patch does not implement support for using both types of devices simultaneously on the same NPU - we expect to add this sometime in the future. Signed-off-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Acked-by: Reza Arbab <arbab@linux.ibm.com> Reviewed-by: Alistair Popple <alistair@popple.id.au> Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
2018-06-27occ: Move occ declarations into occ.hAndrew Donnellan1-27/+0
OCC declarations are currently split between skiboot.h and occ-sensor.h. Given the growing unwieldyness of skiboot.h it's probably time to move it all into one header. Rename occ-sensor.h to occ.h, move all OCC-related declarations out of skiboot.h, and add #includes as necessary. Signed-off-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Reviewed-by: Shilpasri G Bhat <shilpa.bhat@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
2018-06-18Split debug_descriptor out into own include fileStewart Smith1-35/+0
We only touch it in limited places, let's simplify skiboot.h Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
2018-04-30Move P8 timer code to separate fileVasant Hegde1-6/+0
Lets move P8 timer support code from slw.c to sbe-p8.c (as suggested by BenH). There is a difference between timer support in P8 and P9. Hence I think it makes sense to name it as sbe-p8.c. Note that this is pure code movement and renaming functions/variables. No functionality changes. Suggested-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
2018-04-19sensors: Dont add DTS sensors when OCC inband sensors are availableShilpasri G Bhat1-1/+1
There are two sets of core temperature sensors today. One is DTS scom based core temperature sensors and the second group is the sensors provided by OCC. DTS is the highest temperature among the different temperature zones in the core while OCC core temperature sensors are the average temperature of the core. DTS sensors are read directly by the host by SCOMing the DTS sensors while OCC sensors are read and updated by OCC to main memory. Reading DTS sensors by SCOMing is a heavy and slower operation as compared to reading OCC sensors which is as good as reading memory. So dont add DTS sensors when OCC sensors are available. Signed-off-by: Shilpasri G Bhat <shilpa.bhat@linux.vnet.ibm.com> Acked-by: Vaidyanathan Srinivasan <svaidy@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
2018-03-01npu2-opencapi: Configure NPU for OpenCAPIAndrew Donnellan1-0/+1
Scan the device tree for NPUs with OpenCAPI links and configure the NPU per the initialisation sequence in the NPU OpenCAPI workbook. Training of individual links and setup of per-AFU/link configuration will be in a later patch. Signed-off-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Signed-off-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com> Reviewed-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2018-02-21sensor-groups: occ: Add support to disable/enable sensor groupShilpasri G Bhat1-1/+2
This patch adds a new opal call to enable/disable a sensor group. This call is used to select the sensor groups that needs to be copied to main memory by OCC at runtime. Signed-off-by: Shilpasri G Bhat <shilpa.bhat@linux.vnet.ibm.com> [stewart: rebase and bump OPAL API number] Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2018-02-21sensors: Support reading u64 sensor valuesShilpasri G Bhat1-1/+1
This patch adds support to read u64 sensor values. This also adds changes to the core and the backend implementation code to make this API as the base call. Host can use this new API to read sensors upto 64bits. This adds a list to store the pointer to the kernel u32 buffer, for older kernels making async sensor u32 reads. Signed-off-by: Shilpasri G Bhat <shilpa.bhat@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2018-02-21dt: add /cpus/ibm, powerpc-cpu-features device tree bindingsNicholas Piggin1-0/+5
This is a new CPU feature advertising interface that is fine-grained, extensible, aware of privilege levels, and gives control of features to all levels of the stack (firmware, hypervisor, and OS). The design and binding specification is described in detail in doc/. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> [stewart: fix maybe-uninitialized warning from older GCC, doc cleanup] Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2018-02-08core/init: manage MSR[ME] explicitly, always enableNicholas Piggin1-0/+2
The current boot sequence inherits MSR[ME] from the IPL firmware, and never changes it. Some environments disable MSR[ME] (e.g., mambo), and others can enable it (hostboot). This has two problems. First, MSR[ME] must be disabled while in the process of taking over the interrupt vector from the previous environment. Second, after installing our machine check handler, MSR[ME] should be enabled to get some useful output rather than a checkstop. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2018-02-08core/utils: add snprintf_symbolNicholas Piggin1-2/+1
get_symbol is difficult to use. Add snprintf_symbol helper which prints a symbol into a buffer with length, and returns the number of bytes used, similarly to snprintf. Use this in the stack dumping code rather than open-coding it. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2018-01-14SCOM restore for DARN and XIVEAkshay Adiga1-0/+4
While waking up from stop11, we want NCU_DARN_BAR to have enable bit set. Without this stop_api call, the value restored is without enable bit set. We loose NCU_SPEC_BAR when the quad goes into stop11, stop_api will restore while waking up from stop11. Signed-off-by: Akshay Adiga <akshay.adiga@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2018-01-14SLW: Detect if deep states are enabledAkshay Adiga1-0/+1
Patch adds a global variable which indicates if the deep states are enabled through stop-enabled-bits. Only applies to POWER9. Signed-off-by: Akshay Adiga <akshay.adiga@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2018-01-14SLW: Use wakeup_engine state to handle errors in wakeup engineAkshay Adiga1-0/+8
Patch introduces wakeup_engine_state which replaces a bool has_wakeup_engine. wakeup_engine_state can have 3 states : - WAKEUP_ENGINE_PRESENT : When everything is good. - WAKEUP_ENGINE_NOT_PRESENT : When wakeup_engine is not correctly detected. - WAKEUP_ENGINE_FAILED : If any operation on wakeup_engine failed. Signed-off-by: Akshay Adiga <akshay.adiga@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-12-18core/flash.c: extern function to get the name of a PNOR partitionClaudio Carvalho1-0/+1
This adds the flash_map_resource_name() to allow skiboot subsystems to lookup the name of a PNOR partition. Thus, we don't need to duplicate the same information in other places (e.g. libstb). Signed-off-by: Claudio Carvalho <cclaudio@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-12-18libflash/test: Add tests for mbox-flashCyril Bur1-0/+2
A first basic set of tests for mbox-flash. These tests do their testing by stubbing out or otherwise replacing functions not in libflash/mbox-flash.c. The stubbed out version of the function can then be used to emulate a BMC mbox daemon talking to back to the code in mbox-flash and it can ensure that there is some adherence to the protocol and that from a blocklevel api point of view the world appears sane. This makes these tests simple to run and they have been integrated into `make check`. The down side is that these tests rely on duplicated feature incomplete BMC daemon behaviour. Therefore these tests are a strong indicator of broken behaviour but a very unreliable indicator of correctness. Full integration tests with a 'real' BMC daemon are probably beyond the scope of this repository. Signed-off-by: Cyril Bur <cyril.bur@au1.ibm.com> [stewart: fix TESTS_LOOPS printf] Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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