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2019-10-22npu2-opencapi: Improve error reporting to the OSFrederic Barrat2-4/+24
When resetting an opencapi link, the brick will be fenced temporarily. Therefore we can't rely on the fencing state of the brick any more to check for the health of an opencapi PHB, as we could report errors if queried for a PHB state at the same time a link is being reset. Instead, we flag the device as 'broken' when an error interrupt is received, just before raising an event to the OS. When the OS is querying for the state of a PHB, we only have to look at the 'broken' attribute. Note that there's no recovery possible on P9 when an error interrupt is received unexpectedly, as recovery is not supported by hardware. So when a device/link is marked as 'broken', it stays broken. All the OS can do is log the error and notify the drivers. Reviewed-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-10-22npu2-opencapi: Detect PHY reset errorsFrederic Barrat2-4/+16
PHY reset can fail! Though past problems are now fixed, let's handle any future failure. Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Reviewed-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-10-22npu2-opencapi: Simplify freset statesFrederic Barrat1-13/+3
Let's get rid of one transitional state, since there's no need to pause in between releasing the reset signals of the ODL and the adapter. Reviewed-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Reviewed-by: Andrew Donnellan <ajd@linux.ibm.com> Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-10-22npu2-opencapi: Tweak fundamental reset sequenceFrederic Barrat1-22/+26
Modify slightly the ordering of a few steps in our init sequence on fundamental reset, so that it can be called from the OS, when the link is already up: - when the card is reset, the link goes down, so we need to fence the brick to prevent errors propagating to the NPU and OS - since fencing and unfencing don't require any delay, let's also fence/unfence during the very first reset at boot. It's useless but doesn't hurt and keep the code simpler. - resetting the PHY must be done a bit later, while fenced and the ODL and DLx in reset Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Reviewed-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-10-22npu2-opencapi: Rework link training timeoutFrederic Barrat1-4/+5
Opencapi link state should be polled for up to 3 seconds. Current code assumes a tight retry loop during fundamental reset at boot, which is not going to be true on link retraining. So update the timeout detection code to use a timebase instead of a simple retry count which could be way too long. Reviewed-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Reviewed-by: Andrew Donnellan <ajd@linux.ibm.com> Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-10-22npu2-hw-procedures: Fix link retraining on resetFrederic Barrat1-0/+16
Link retraining was showing reliability problems due to some opencapi-only settings not being optimized. This patch updates some extra PHY state, as agreed with the PHY team. Though they mostly impact link retraining behavior, they should also be set at boot. Reviewed-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Reviewed-by: Andrew Donnellan <ajd@linux.ibm.com> Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-10-22npu2-opencapi: Make sure the PCI slot has the proper IDFrederic Barrat1-1/+2
The PCI slot created for the opencapi PHB didn't have its ID properly defined because it was created before we assign an ID to the PHB. Simply switch the PCI slot creation and PHB registration calls to fix it. Reviewed-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Reviewed-by: Andrew Donnellan <ajd@linux.ibm.com> Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-10-22npu2-hw-procedures: Move some opencapi PHY settings in one-off initFrederic Barrat1-19/+16
The PHY_RX_AC_COUPLED and PHY_RX_SPEED_SELECT for opencapi are group settings for the obus. They should be set in the one-off PHY init function at boot and not on the link reset path, as they theoretically impact more than one link. Since we cannot mix link type and/or speed on an optical bus, it has no pratical impact, it just looks cleaner. Also use the OCAPIINF macro for the associated traces. Reviewed-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Reviewed-by: Andrew Donnellan <ajd@linux.ibm.com> Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-09-06hw/psi: Remove explicit external IRQ policyOliver O'Halloran1-8/+6
Rather than having an explicit policy use the presence of a platform defined external interrupt handler to determine whether we should direct the interrupt to OPAL or not. This lets us remove a pile of comments about why the policy is necessary and the comments about why we need to un-set it on P8+ Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-09-06hw/psi-p9: Mask OPAL-owned LSIs without handlersOliver O'Halloran2-6/+36
Some versions of Swift have the TPM interrupt line of the second chip pulled up instead of down. This causes the PSI's external (TPM) interrupt to constantly re-fire since it's an LSI and the interrupt signal is constantly active. There's nothing that can be done to clear the underlying interrupt condition so we to ensure that it's masked. The problem isn't really specific to the external interrupt and will occur for any of the PSI interrupts that don't have an actual handler (FSP, global error, and sometimes the external). When one of these is delivered to OPAL we should log that it happened and mask it to prevent re-firing. Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-09-06hw/psi-p9: Make interrupt name array globalOliver O'Halloran1-19/+19
The array of P9 PSI interrupt names is currently a static constant inside psi_p9_irq_name(). We'd like to use these names in another function so move it outside. Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Reviewed-by: Cédric Le Goater <clg@kaod.org>
2019-09-06hw/psi: Add chip ID to interrupt namesOliver O'Halloran1-23/+33
Each chip has a separate PSI, but the interrupt names are the same for both. Add the chip ID to the interrupt name of each to help differentiate between the two. Before: $ ./count_irqs.py |grep psi:i2c 27: 13006 - XIVE-IRQ 2097147 Level opal-psi:i2c 507: 3447 - XIVE-IRQ 1048571 Level opal-psi:i2c After: $ ~/count_irqs.py |grep i2c 27: 4338 - XIVE-IRQ 2097147 Level opal-psi#8:i2c 507: 11668 - XIVE-IRQ 1048571 Level opal-psi#0:i2c Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Reviewed-by: Cédric Le Goater <clg@kaod.org>
2019-09-06xive: fix return value of opal_xive_allocate_irq()Cédric Le Goater1-1/+1
When the maximum number of interrupts per chip is reached, xive_try_allocate_irq() returns an internal XIVE error: XIVE_ALLOC_NO_SPACE. But its value 0xffffffff is interpreted as a positive value by its caller opal_xive_allocate_irq() and not as an error. opal_xive_allocate_irq() returns this value to Linux which also considers 0xffffffff as a valid interrupt number and tries to get the interrupt characteritics using opal_xive_get_irq_info(). This OPAL calls finally fails leading to all sort of errors on the host which is not prepared for such a scenario. Code impacted are the IPI setup and the both XIVE KVM devices. Fix by returning OPAL_RESOURCE from xive_try_allocate_irq() which is consistent with the other errors returned by this routine. This fixes the behavior in opal_xive_allocate_irq() and in Linux. A workaround could be introduced in Linux to consider 0xffffffff as a OPAL_RESOURCE value. This assumption is valid with the current XIVE IRQ number encoding. Fixes: 07946e68f47a ("xive: Add interrupt allocator") Reported-by: Greg Kurz <groug@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org> [oliver: Added fixes tag] Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-09-06hw/test: include -gcov binaries in clean targetEric Richter1-1/+1
This patch fixes an oversight in the hw-clean make target that removes the .gcno object, but does not remove the -gcovr test binary. Therefore, the .gcno object is not recreated on a subsequent coverage-report build, which causes an error that fails the build. Signed-off-by: Eric Richter <erichte@linux.ibm.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-09-06slw: Enable stop states on P9PRyan Grimm1-1/+2
Enable stop states on P9P for the Swift platform. Signed-off-by: Ryan Grimm <grimm@linux.ibm.com> [oliver: fixed patch title] Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-08-23hw/lpc: Configure SerIRQ interrupts on P9POliver O'Halloran1-2/+5
We need to do the LPC SerIRQ mux configuration on P9P too. Without this we don't get UART interrupts from the BMC which makes the UART console *much* less responsive than it should be. Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-08-23npu3: Delay enablement of DL parity checkingReza Arbab2-6/+8
Currently, we turn on TX and PRI parity checking of the DL during NPU initialization, while RX parity checking is not enabled until after link training. This behavior was prescribed for npu2, but on npu3 systems the logic has changed such that we're getting early parity error checkstops. To fix, only set the TX and PRI enable bits after training, consistent with RX. Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
2019-08-23pci: recheck pci nvram hacks on fast-rebootOliver O'Halloran1-2/+0
Sometimes it's useful to fiddle with some of the PCI NVRAM options that we have. Currently this is mostly for enabling and disabling pci-tracing mode, but having a common place for this stuff is a good idea. Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Reviewed-by: Alexey Kardashevskiy <aik@ozlabs.ru>
2019-08-23npu2: Invalidate entire TCE cache if many entries requestedAlexey Kardashevskiy1-5/+12
Turned out invalidating entries in NPU TCE cache is so slow that it becomes visible when running a 30+GB guest with GPU+NVlink2 passed through; a 100GB guest takes about 20s to map all 100GB. This falls through to the entire cache invalidation if more than 128 TCEs were requested to invalidate, this reduces 20s from the abobe to less than 1s. The KVM change [1] is required to see this difference. The threshold of 128 is chosen in attempt not to affect performance much as it is not clear how expensive it is to populate the TCE cache again; all we know for sure is that mapping the guest produces invalidation requests of 512 TCEs each. Note TCE cache invalidation in PHB4 is faster and does not require the same workaround. [1] KVM: PPC: vfio/spapr_tce: Split out TCE invalidation from TCE updates https://patchwork.ozlabs.org/patch/1149003/ Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: Alistair Popple <alistair@popple.id.au>
2019-08-16ipmi: Use standard MIN() macro definitionJordan Niethe1-3/+1
There is a MIN() macro definition in skiboot.h. Remove the redundant definition from here and use that one. Signed-off-by: Jordan Niethe <jniethe5@gmail.com> Acked-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-08-16hw/phb4: Use standard MIN/MAX macro definitionsJordan Niethe1-6/+3
The max() macro definition incorrectly returns the minimum value. The max() macro is used to ensure that PERST has been asserted for 250ms and that we wait 100ms seconds for the ETU logic in the CRESET_START PHB4 PCI slot state. However, by returning the minimum value there is no guarantee that either of these requirements are met. Correct macro definitions for MIN and MAX are already provided in skiboot.h. Remove the redundant/incorrect versions here and switch to using the standard ones. Fixes: 70edcbb4b39d ("hw/phb4: Skip FRESET PERST when coming from CRESET") Signed-off-by: Jordan Niethe <jniethe5@gmail.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-08-16hw/phb4: Prevent register accesses when in resetOliver O'Halloran1-0/+10
While the the ETU is in reset we cannot access any of the PHB registers. If a PHB register is accessed via the XSCOM indirect interface then we'll cause an ETU reset error which may prevent the PHB from being re-initialised once the reset is lifted. Prevent register accesses while in reset by adding a flag that is set while the ETU reset bit is high and checking that flag in the XSCOM (ASB) backdoor register access path. Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-08-16npu: Fix device binding error messageReza Arbab1-2/+6
Helping someone troubleshoot a Garrison machine, I noticed some of the BDFs printed here are wrong: npu_dev_bind_pci_dev: No PCI device for NPU device 0004:00:00.0 to bind to. If you expect a GPU to be there, this is a problem. npu_dev_bind_pci_dev: No PCI device for NPU device 0004:00:01.0 to bind to. If you expect a GPU to be there, this is a problem. npu_dev_bind_pci_dev: No PCI device for NPU device 0004:00:04.0 to bind to. If you expect a GPU to be there, this is a problem. npu_dev_bind_pci_dev: No PCI device for NPU device 0004:00:05.0 to bind to. If you expect a GPU to be there, this is a problem. Change the prlog() call to print them correctly. Signed-off-by: Reza Arbab <arbab@linux.ibm.com> Reviewed-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-08-16npu3: Expose remaining ATSD launch registersReza Arbab1-9/+12
List all 16 ATSD registers in the device tree, not just the first 8. Signed-off-by: Reza Arbab <arbab@linux.ibm.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-08-16npu3: Initialize NPU3_SNP_MISC_CFG0Reza Arbab1-0/+7
Enable powerbus snooping here, or else MMIO to any NTL/NDL registers will cause a checkstop. This was not an issue in Simics simulation, but discovered rather quickly during bringup on a real Axone chip. Signed-off-by: Reza Arbab <arbab@linux.ibm.com> Reviewed-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-08-16npu3: Rename NPU3_SM_MISC_CFGn register macrosReza Arbab1-5/+5
The SM blocks have multiple MISC_CFG registers. For example, there are both CS.SM0.MCP.MISC.CONFIG0 and CS.SM0.SNP.MISC.CONFIG0. Rename our macro for the former to more clearly reflect this and avoid a clash when the latter is added. Signed-off-by: Reza Arbab <arbab@linux.ibm.com> Reviewed-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-08-16pci: Use a macro for accessing PCI BDF Function NumberJordan Niethe3-8/+8
Currently when the Function Number bits of a BDF are needed the bit operations to get it are free coded. There are many places where the Function Number is used, so make a macro to use instead of free coding it everytime. Signed-off-by: Jordan Niethe <jniethe5@gmail.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-08-16pci: Use a macro for accessing PCI BDF Device NumberJordan Niethe2-4/+4
Currently when the Device Number bits of a BDF are needed the bit operations to get it are free coded. There are many places where the Device Number is used, so make a macro to use instead of free coding it everytime. Signed-off-by: Jordan Niethe <jniethe5@gmail.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-08-16pci: Use a macro for accessing PCI BDF Bus NumberJordan Niethe4-11/+11
Currently when the Bus Number bits of a BDF are needed the bit operations to get it are free coded. There are many places where the Bus Number is used, so make a macro to use instead of free coding it everytime. Signed-off-by: Jordan Niethe <jniethe5@gmail.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-08-16include/xscom: Use the name EQ rather than EPOliver O'Halloran1-6/+6
The P9 pervasive spec uses the term "EP" to refer to the combination of an EQ chiplet and its two child EX chiplets. Nothing else seems to use the term EP and in Skiboot all the uses of the XSCOM_ADDR_P9_EP() macro are to translate the address of EQ specific SCOM registers. Change the name of our address calculation macros to match the general terminology to make what it does clearer. Cc: Anju T Sudhakar <anju@linux.vnet.ibm.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-08-15HIOMAP: Reset bmc mbox in MPIPL pathVasant Hegde1-0/+6
During boot SBE and early hostboot does not use HIOMAP protocol to get image from PNOR. Instead it expects PNOR TOC and Hostboot Boot Loader to be available at particular address in LPC bus. mbox daemon in BMC side takes care of this during normal boot. Once boot is complete mbox daemon switches to normal mode. During normal reboot, BMC side mbox daemon gets notification and takes care of loading PNOR TOC and HBBL to LPC bus again. In MPIPL path, OPAL calls SBE S0 interrupt to initiate MPIPL. BMC will not be aware of this. But SBE expects PNOR TOC and HBBL to be available in LPC bus at predefined address. Hence call HIOMAP Reset from OPAL in assert path. This needs working LPC and IPMI driver in OPAL. If we have issue in these drivers then we may not be able to reset BMC MBOX properly. Hence MPIPL may fail. We have to live with this until we find a way to intiate BMC on MPIPL. CC: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> [oliver: rebased] Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-08-15MPIPL: Save crashing PIRVasant Hegde1-0/+4
Crashing CPU PIR is required to get proper backtrace from core file. Save crashing CPU PIR before triggering MPIPL. Post MPIPL OPAL will pass saved PIR to kernel and kernel will use that to create OPAL dump. Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> [oliver: rebased] Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-08-15MPIPL: Add support to trigger MPIPL on BMC systemVasant Hegde2-3/+74
On FSP based system we call 'attn' instruction. FSP detects attention and initiates memory preserving IPL. On BMC system we have to call SBE S0 interrupt to initiate memory preserving IPL. This patch adds support to call SBE S0 interrupt in assert path. Sequence : - S0 interrupt on secondary chip SBE - S0 interrupt on primary chip SBE Note that this is hooked to ipmi_terminate path. We have HDAT flag for MPIPL support. If MPIPL is not supported then we don't create 'ibm,opal/dump' node and we will fall back to existing termination flow. Finally we want to log error log to BMC before triggerring MPIPL. Hence this patch re-organizes ipmi_terminate() such that we call ipmi_log_terminate_event() before triggering MPIPL. Note: - At present we do not have a proper way to detect SBE is alive or not. So we wait for predefined time and then call normal reboot. Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> [oliver: rebased] Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-08-15SBE: Send OPAL relocated base address to SBEVasant Hegde1-0/+48
OPAL relocates itself during boot. During memory preserving IPL hostboot needs to access relocated OPAL base address to get MDST, MDDT tables. Hence send relocated base address to SBE via 'stash MPIPL config' chip-op. During next IPL SBE will send stashed data to hostboot... so that hostboot can access these data. Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> [oliver: rebased] Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-08-15hdata: Split MDST 'type' field to accommodate MPIPLVasant Hegde1-4/+4
The MPIPL facility needs to store region and type information corresponding with each MDST entry. - data region : dump data regions (like DUMP_REGION_* ) - dump type : Reflects MDST entry usage (used by SYSDUMP -OR- FADUMP) The existing type field is currently not used by FSP and/or firmware, so it is safe to re-purpose it. Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> [oliver: rebased] Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-08-15FSP/MDST: Rename fsp-mdst-table.c -> fsp-sysdump.cVasant Hegde2-4/+4
MDST is a ntuple inside SPIRAH. Its just a interface to pass memory ranges to be captured as part of dump to FSP/Hostboot. Today OPAL is using MDST ntuple to pass list of memory region (mostly OPAL console and host dmesg) to be collected as part of SYSDUMP. Soon we are going to support OPAL MPIPL feature (aka Memory Preserving IPL). Even MPIPL uses MDST/MDDT table. Hence rename files based on feature instead of some table name: - fsp-mdst-table.c -> fsp-sysdump.c - fsp-mdst-table.h -> opal-dump.h (This will cater both SYSDUMP and MPIPL) - Rename structure -> dump_mdst_table -> mdst_table This patch does renaming and header file adjustment. No functionality changes. Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> [oliver: rebased] Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-08-02occ: Add pstate corresponding to base frequency to DTShilpasri G Bhat1-0/+2
Unlike POWER8, nominal frequency is not the highest guaranteed frequency of the POWER9 chip. In POWER9, the highest guaranteed frequency is greater than the nominal frequency and is referred to as base frequency. In POWER9 base frequency is the highest frequency the processor will operate at when ALL cores are active and in ANY operating condition. This patch exports the turbo pstate as the base frequency as per OCC documentation. Signed-off-by: Shilpasri G Bhat <shilpa.bhat@linux.vnet.ibm.com> [oliver: delete ibm,pstate-base on fast reboot] Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-08-02hw/sbe-p9: Fix multi-line log messagesOliver O'Halloran1-3/+3
When sending messages to the SBE we log the message using a multi-line log message that looks like this: [ 96.390873752,8] SBE: Message queued [chip id = 0x0]: Reg0 : 000002010054d401 Reg1 : 0000000000030d40 Reg2 : 0000000000000000 Reg3 : 0000000000000000 The lack of a common prefix makes the log messages annoying to deal with since you can just grep for SBE: to get all the SBE related messages, and you can't use grep -v to remove them. There's no real benifit to squashing all this into a single prlog() call, so use a for loop to print the registers. With this patch the output is: [ 93.253511545,8] SBE: Message queued [chip id = 0x0]: [ 93.253512343,8] SBE: Reg0 : 000002010059d401 [ 93.253513167,8] SBE: Reg1 : 0000000000030d40 [ 93.253513894,8] SBE: Reg2 : 0000000000000000 [ 93.253514627,8] SBE: Reg3 : 0000000000000000 Cc: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Acked-by: Stewart Smith <stewart@linux.ibm.com> Reviewed-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2019-07-30Support BMC IPMI heartbeat commandAndrew Geissler1-0/+14
A few years ago, the OpenBMC code added support for a "heartbeat" command to send to the host. This command is used after the BMC is reset to check if the host is running. Support was never added to the host side however so currently when the BMC sends this command, this appears in the host console: IPMI: unknown OEM SEL command ff received There is no response needed by the host (other then the low level acknowledge of the command which already occurs). This commit handles the command so the error is no longer printed (does nothing with the command though since no action is needed). Here's the tested output of this patch in the host console (with debug enabled): IPMI: BMC issued heartbeat command: 00 Signed-off-by: Andrew Geissler <geissonator@yahoo.com>
2019-07-30hw: Put SPDX on new filesOliver O'Halloran5-70/+15
Convert the npu3 files to use SPDX headers. Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-07-26hw: Introduce npu3Reza Arbab5-9/+3214
POWER9P systems have been upgraded with NVLink 3.0 interconnects. The underlying hardware is fundamentally different--each POWER9 chip has (1 NPU) * (3 stacks) * (2 bricks) = (6 links) Where in each POWER9P chip, there are (3 NPUs) * (4 bricks) = (12 links) This flatter hierarchy simplifies the firmware implementation a bit, but also prevents sharing much common code with npu2. As in previous versions, initialize the hardware and expose each link to the OS as a virtual PCIe device. This initial support covers NVLink devices only, with OpenCAPI to follow. Signed-off-by: Reza Arbab <arbab@linux.ibm.com> Reviewed-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-07-26npu2: Add checks to npu2-only codepathsReza Arbab1-0/+4
To prepare for npu3, add a few checks in codepaths that are only for npu2. Compare against PVR_TYPE_P9, as npu3 will be in systems of PVR_TYPE_P9P (or greater). Alternatively, check for dt compatibility with "ibm,power9-npu" because npu3 will use "ibm,power9-npu3". Signed-off-by: Reza Arbab <arbab@linux.ibm.com> Reviewed-by: Andrew Donnellan <ajd@linux.ibm.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-07-26npu2: Refactor NPU OPAL callsReza Arbab3-132/+183
Abstract the OPAL entry points for npu2, moving them to a new file. This prepares us to add parallel npu3 versions of the same APIs. No functional change. Signed-off-by: Reza Arbab <arbab@linux.ibm.com> Reviewed-by: Andrew Donnellan <ajd@linux.ibm.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-07-26npu2: Prepare purge_l2_l3_caches() for reuseReza Arbab3-139/+175
Move this to a separate compilation unit with its own header, for reuse. The code formerly in npu2.c is copied verbatim. The #defines formerly in npu2-regs.h have been reformatted and changed to use PPC_BITMASK() instead of multiple consecutive PPC_BIT()s. Signed-off-by: Reza Arbab <arbab@linux.ibm.com> Reviewed-by: Andrew Donnellan <ajd@linux.ibm.com> Reviewed-by: Alexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: Stewart Smith <stewart@linux.ibm.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-07-26hw/phys-map: Add Axone memory mapReza Arbab2-3/+139
Add the physical memory map for Axone systems. According to 'make hw-check', there are no holes or overlapping regions. Signed-off-by: Reza Arbab <arbab@linux.ibm.com> Acked-by: Michael Neuling <mikey@neuling.org> Reviewed-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Reviewed-by: Andrew Donnellan <ajd@linux.ibm.com> Acked-by: Stewart Smith <stewart@linux.ibm.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-07-26hw/phys-map: Add pvr argument to phys_map_init()Reza Arbab2-5/+13
When new chip types are added, phys_map_init() will need to know which memory map it should use. Instead of directly checking PVR, make it an argument to the function, so that 'make hw-check' can test all the maps. Signed-off-by: Reza Arbab <arbab@linux.ibm.com> Acked-by: Michael Neuling <mikey@neuling.org> Reviewed-by: Andrew Donnellan <ajd@linux.ibm.com> Acked-by: Stewart Smith <stewart@linux.ibm.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-07-26Dedup $(HW_OBJS)Reza Arbab1-4/+2
How did I notice one dup in aa56d9a2abdb ("Remove duplicate npu-common.o from $(HW_OBJS)"), but not the other five? Remove them too. Signed-off-by: Reza Arbab <arbab@linux.ibm.com> Reviewed-by: Alistair Popple <alistair@popple.id.au> Reviewed-by: Andrew Donnellan <ajd@linux.ibm.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-07-26SPDX-ify all skiboot codeStewart Smith83-1149/+321
Use Software Package Data Exchange (SPDX) to indicate license for each file that is unique to skiboot. At the same time, ensure the (C) who and years are correct. See https://spdx.org/ Signed-off-by: Stewart Smith <stewart@linux.ibm.com> [oliver: Added a few missing files] Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-07-19Move ec/ code to Rhesus platformStewart Smith4-104/+0
The embedded controller that Rhesus uses is exclusive to that platform, make it purely part of tha platform Signed-off-by: Stewart Smith <stewart@linux.ibm.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-07-19sparse: lpc uart interrupt pointer endiannessStewart Smith1-1/+1
hw/lpc-uart.c:674:47: warning: incorrect type in argument 1 (different base types) hw/lpc-uart.c:674:47: expected restricted beint32_t [usertype] be_val hw/lpc-uart.c:674:47: got unsigned int const [usertype] Signed-off-by: Stewart Smith <stewart@linux.ibm.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
generated by cgit v1.1 at 2025-09-19 03:25:34 +0000