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2023-11-27hw/imc: Detect BML and fix core countersRyan Grimm1-5/+5
On systems running BML we started noticing this in the skiboot log: [ 409.088819302,3] XSCOM: write error gcid=0x0 pcb_addr=0x20000060 stat=0x4 [ 409.088823446,3] ELOG: Error getting buffer to log error [ 409.088824806,3] XSCOM: Write failed, ret = -26 [ 409.088825797,3] IMC: error in xscom_write for pdbar [ 0.468976][ T19] core_imc memory allocation for cpu 0 failed [ 0.468993][ T1] IMC PMU core_imc Register failed I tracked down that bad pcb_addr to this line in the code: pdbar_addr = get_imc_scom_addr_for_quad(phys_core_id, pdbar_scom_index[port_id]); I found that pdbar_scom_index was not initialized because, like mambo, we don't have the IMC catalog in memory. So, in imc_init we error out and never initialize it in setup_imc_scoms. This patch adds a chip quirk QUIRK_BML because it seems like a reasonable thing to do and it's easy to put a BML {}; in the device tree like Mambo, Awan, etc. It is tested on a Rainier and errors are gone and /sys/devices/core_imc shows up as expected. Signed-off-by: Ryan Grimm <grimm@linux.ibm.com> Reviewed-By: Madhavan Srinivasan <maddy@linux.ibm.com>
2023-10-11hdata: Remove legacy SPIRA structureNicholas Piggin1-1/+0
skiboot only supports POWER8 > DD1 now, all supported platforms should use the new SPIRA-S/H structure. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
2023-09-15hw/imc: Update IMC PMU node names for power10Athira Rajeev1-10/+186
The nest IMC (In Memory Collection) Performance Monitoring Unit(PMU) node names are saved as "struct nest_pmus_struct" in the "hw/imc.c" IMC code. Not all the IMC PMUs listed in the device tree may be available. Nest IMC PMU names along with their bit values is represented in imc availability vector. This struct is used to remove the unavailable nodes by checking this vector. For power10, the imc_chip_avl_vector ie, imc availability vector ( which is a part of the IMC control block structure ), has change in mapping of units and bit positions. Hence rename the existing nest_pmus array to nest_pmus_p9 and add entry for power10 as nest_pmus_p10. Also the avl_vector has another change in bit positions 11:34. These bit positions tells the availability of Xlink/Alink/CAPI. There are total 8 links and three bit field combination says which link is available. Patch implements all these change to handle nest_pmus_p10. Signed-off-by: Athira Rajeev <atrajeev@linux.vnet.ibm.com> Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
2023-09-15hw/imc: Update IMC code to use dt_find_by_name_before_addr for checking dt nodesAthira Rajeev1-9/+9
The nest IMC (In Memory Collection) Performance Monitoring Unit(PMU) node names are saved in nest_pmus[] array in the "hw/imc.c" IMC code. Not all the IMC PMUs listed in the device tree may be available. Nest IMC PMU names along with their bit values is represented in imc availability vector. The nest_pmus[] array is used to remove the unavailable nodes by checking this vector. To check node availability, code was using "dt_find_by_substr". But since the node names have format like: "name@offset", dt_find_by_name doesn't return the expected result. Fix this by using dt_find_by_name_before_addr. Also, update the char array to use correct node names. Signed-off-by: Athira Rajeev <atrajeev@linux.vnet.ibm.com> Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
2023-09-12core/pldm: PLDM over MCTP BindingChristophe Lombard1-0/+18
Enable the mctp binding over LPC bus interface and new wrappers to send and receive PLDM messages over the mctp library. PLDM is supported as a message type over MCTP. PLDM over MCTP binding defines the format of PLDM over MCTP messages. An MCTP Endpoint is the terminus for MCTP communication. A physical device that supports MCTP may provide one or more MCTP Endpoints. Endpoints are addressed using a logical address called the Endpoint ID, or EID. EIDs in MCTP are analogous to IP Addresses in Internet Protocol networking. The BMC EID default is 8. First byte of the PLDM over MCTP Message Fields identifies the MCTP message as carrying a PLDM message: Message Type (7 bits) PLDM = 0x01 (000_0001b). Reviewed-by: Abhishek Singh Tomar <abhishek@linux.ibm.com> Signed-off-by: Christophe Lombard <clombard@linux.ibm.com> Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
2023-09-12hw/ast-bmc: Initialize ast lpc mctp bindingChristophe Lombard2-0/+371
The Management Component Transport Protocol (MCTP) defines a communication model intended to facilitate communication. This patch initialize MCTP binding over LPC Bus interface. Several steps must be performed: - Initialize the MCTP core (mctp_init()). - Initialize a hardware binding as AST LPC mode host (mctp_astlpc_init()). - Register the hardware binding with the core (mctp_register_bus()), using a predefined EID (Host default is 9). To transmit a MCTP message, mctp_message_tx() is used. To receive a MCTP message, a callback need to be provided and registered through mctp_set_rx_all(). For the transfer of MCTP messages, two basics components are used: - A window of the LPC FW address space, where reads and writes are forwarded to BMC memory. - An interrupt mechanism using the KCS interface. hw/ast-bmc/ast-mctp.c is compilated if the compiler flag CONFIG_PLDM is set. Reviewed-by: Abhishek Singh Tomar <abhishek@linux.ibm.com> Signed-off-by: Christophe Lombard <clombard@linux.ibm.com> Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
2023-09-12hw: Move lpc firmware space helpersChristophe Lombard1-0/+74
Add new lpc helpers for doing a bulk io to firmware space. Reviewed-by: Abhishek Singh Tomar <abhishek@linux.ibm.com> Signed-off-by: Christophe Lombard <clombard@linux.ibm.com> Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
2023-07-12psi: Remove PSIHB_XIVR referenceJoel Stanley1-2/+0
The define for PSIHB_XIVR was removed with P7 support. Signed-off-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
2023-07-11hw/chiptod: allow qemu to use the chiptodNicholas Piggin1-2/+6
There is a QEMU model for ChipTOD (not yet upstream) that provides enough to get through skiboot's sync sequence. So run the chiptod init when running under QEMU, if it is being provided in the device tree. If not, don't crash because the QEMU patch has not been merged yet... Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
2023-06-06ipmi: remove unused OS watchdog supportNicholas Piggin1-25/+0
This code hasn't been enabled, remove it. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
2023-06-06ipmi: flush the ipmi message queue before booting a kernelNicholas Piggin2-3/+16
Bring ipmi to a consistent state before booting a kernel by flushing all outstanding messages. The OS may not start kicking the IPMI state machine for some time. For example, without this change, when booting in QEMU, the IPMI command issued by ipmi_wdt_final_reset() to disable the watchdog is not sent to the BMC before the OS boots, effectively leaving the watchdog enabled until the OS begins to drive OPAL pollers. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Reviewed-by: Stewart Smith <stewart@flamingspork.com> Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
2023-06-06platforms: Use astbmc_exitNicholas Piggin1-1/+0
Move all platforms using astbmc_init() to use astbmc_exit(). Move ipmi_set_boot_count() to astbmc_exit from ipmi_wdt_final_reset(). Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
2023-06-06VAS: use local_free to free local_alloc memoryNicholas Piggin1-2/+2
free() asserts because local_alloc() doesn't allocate from the skiboot heap region. Fix this by using local_free(). Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
2023-02-27hw/phb4: Clear the PEC FIRs when taking the ETU out of resetFrederic Barrat1-13/+17
The documented PEC recovery procedure is to clear the PEC FIR registers when the ETU/PHB is in reset. However, any xscom access targeting a PHB register while it is in reset will raise a new error (PFIR bit 3), so it is possible to get out of reset and still have a FIR register showing errors. It has been observed that the OCC, through its 24x7 service, can do such a xscom access at boot time if we end up in the CRESET path. So the current behavior of logging an error is not desirable. The recommendation from the logic designer is to keep the existing mechanism to clear the FIR registers and add an extra step to clear any new errors immediately after taking the ETU out of reset. That's what this patch is doing. Fixes: https://github.com/open-power/skiboot/issues/273 Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
2023-02-27hw/phb4: Use symbols when accessing PEC registersFrederic Barrat1-12/+18
This patch improves readability just a tiny bit by using symbols, most of them already existing, instead of values when accessing the PEC registers. No functional changes. Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
2022-07-05interrupts: Speed up opal interrupts scanningFrederic Barrat2-0/+20
When looking for which interrupts are serviced by opal, we scan all sources and query every single interrupt to know if it's for linux or opal. An optimization was made so that if the source doesn't have an 'interrupt' op (=the handler) or an 'attributes' op (to do the query), then we can skip the source. That's all good. However, when xive was introduced, the 'irq_source' defining those ops was wrapped in a 'xive_src' source which adds a level of indirection for those 'attributes' and 'interrupt' ops. So the previous optimization no longer works: the 'attributes' and 'interrupt' ops are defined from the wrapper, but if we could look past the indirection, we would realize they are not. That is getting problematic for the rather large generic IPIs source. We have 8 million such interrupts defined per chip on P10 and because the above optimization is no longer kicking in, we are now querying every single one of them to know if it is for opal. Real hardware swallows it without much difficulty, but simulators don't. Running qemu on my laptop, the full scan takes ~12 seconds per chip! This patch adds a callback for an interrupt source to report whether it has opal interrupts. If the source doesn't define it, then we fallback to looking at the 'interrupt' and 'attributes' ops, like before, as it is still useful on P8. We can then define that new callback on the xive sources, allowing to look past the indirection level and skip scanning the source when appropriate. Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
2022-06-13xive: Fix NSR value when dumping the state of thread contextFrederic Barrat2-2/+2
There's no reason to skip 2 bits when printing the Notification Source Register (NSR) of any thread context ring. So it's got to be a silly mistake and we should shift by 56 bits and not 58 :-) Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Reviewed-by: Dan Horák <dan@danny.cz> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
2022-06-13fsp: Fix possible use of null "%s" prlog argumentReza Arbab1-1/+3
Caught by CI in fedora-rawhide (GCC 12): hw/fsp/fsp-codeupdate.c:116:26: error: '%s' directive argument is null [-Werror=format-overflow=] 116 | prlog(PR_NOTICE, "CUPD: IPL SIDE = %s\n", side); To prevent this, explicitly print the value of ipl_side instead. Signed-off-by: Reza Arbab <arbab@linux.ibm.com> Reviewed-by: Dan Horák <dan@danny.cz>
2022-05-23xscom: Parse P10 ec revisionJoel Stanley1-18/+19
Use a look up table to support the p9, p10dd1 and p10dd2 conversions. Running on a Rainier: > [ 268.267370706,6] CPU: P10 generation processor (max 4 threads/core) > [ 268.267372501,7] CPU: Boot CPU PIR is 0x0460 PVR is 0x00801200 > [ 268.284420384,5] CHIP: Chip ID 0000 type: P10 DD2.02 > [ 268.284464084,5] CHIP: Chip ID 0002 type: P10 DD2.02 > [ 268.284500468,5] CHIP: Chip ID 0004 type: P10 DD2.02 > [ 268.284538166,5] CHIP: Chip ID 0006 type: P10 DD2.02 > [ 268.286317879,5] PLAT: Detected Rainier platform Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Dan Horák <dan@danny.cz> Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
2022-05-23xscom: Move p9 ec level parsing to a functionJoel Stanley1-30/+44
In preparation for adding p10 logic. No functional change. Reviewed-by: Dan Horák <dan@danny.cz> Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
2022-02-04Fix array-bound compilation warningsAbhishek Singh Tomar1-1/+1
Resolves : the warray bounds warning during compilation /build/libc/include/string.h:34:16: warning: '__builtin_memset' offset [0, 2097151] is out of the bounds [0, 0] [-Warray-bounds] 34 | #define memset __builtin_memset hw/fsp/fsp.c:1855:9: note: in expansion of macro 'memset' 1855 | memset(fsp_tce_table, 0, PSI_TCE_TABLE_SIZE); use volatile pointer to avoid optimization introduced with gcc-11 on constant address assignment to pointer. Signed-off-by: Abhishek Singh Tomar <abhishek@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-01-03npu: Move npu.o and npu-hw-procedules.o under CONIFG_P8Stewart Smith1-1/+2
Make the P8 NPU code depend on CONFIG_P8. This requires converting a low level function to a no-op because the HMI NPU handling is not so cleanly layered. This saves an extra 6kb of skiboot.lid.xz. Reviewed-by: Dan Horák <dan@danny.cz> Signed-off-by: Stewart Smith <stewart@flamingspork.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-01-03hwprobe: convert vas_init(), nx_init()Stewart Smith2-0/+4
Convert VAS and NX to use the hwprobe facility for init. Reviewed-by: Dan Horák <dan@danny.cz> [npiggin: remove imc_init because it moved later in boot (fbcbd4e47c)] Signed-off-by: Stewart Smith <stewart@flamingspork.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-01-03hw/slw: split P8 specific code into its own fileNicholas Piggin7-481/+523
POWER8 support is large and significantly different than P9/10 code. This change prepares to make P8 support configurable. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> [ clg: Removed commented headers in slw.c ] Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-01-03hw/slw: Move P8 bits behind CONFIG_P8Nicholas Piggin3-86/+96
This saves about 10kB from skiboot.lid.xz Reviewed-by: Dan Horák <dan@danny.cz> Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-01-03SBE: create processor-independent timer APIsNicholas Piggin4-15/+36
Rather than have code call processor-specific SBE routines depending on version, hide those details in SBE APIs. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> [ clg: Fixed run-timer test ] Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-01-03Add CONFIG_P8 with PHB3 behind itStewart Smith1-1/+4
We can use a base CPU of POWER9 if we don't have P8. We can also hide PHB3 code behind this, and shave 12kb off skiboot.lid.xz Reviewed-by: Dan Horák <dan@danny.cz> [npiggin: add cpp define, fail gracefully on P8] Signed-off-by: Stewart Smith <stewart@flamingspork.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-01-03hwprobe: convert PHB, NPU, PAU subsystems to hwprobeStewart Smith5-6/+13
Reviewed-by: Dan Horák <dan@danny.cz> [npiggin: split out from initial hwprobe pach] Signed-off-by: Stewart Smith <stewart@flamingspork.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-12-23chiptod: properly zero TB SPR when cleaning up for invalid TBNicholas Piggin1-1/+2
The existing sequence writes TBU twice and leaves TBL unchanged. This may not really matter if it's being resynced from the chiptod soon, but it's possible it could clear a parity error. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-12-09hw/lpc: fix compilation errorNicholas Piggin1-0/+1
Compilation can fail when building tests if the opal-api.h include is not pulled in via headers. Include it directly. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-12-09ccan: switch list_add_before/after arguments to match upstreamNicholas Piggin1-1/+1
Upstream ccan uses (list, existing entry, new entry) parameter ordering rather than (list, new entry, existing entry) ordering. Switch these to make syncing with upstream simpler. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-10-21xive/p10:: Declare xive2 DT node as an interrupt-controllerFrederic Barrat1-1/+6
This patch fixes errors seen when linux looks for the interrupt to use for a device LSI: pci X:Y:Z of_irq_parse_pci: failed with rc=-22 The of/irq parsing code requires those new properties to be able to map the interrupt specifier correctly. It was not needed before comitting cd12ea6d8e1 ("interrupts: Do not advertise XICS support on P10"), because the LSI mapping code was defaulting to the XICS interrupt controller node, which is now removed (and had those properties). Fixes: cd12ea6d8e1 ("interrupts: Do not advertise XICS support on P10") Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-10-19pau: Add support for OpenCAPI Persistent Memory devices.Christophe Lombard4-16/+137
Lowest Point of Coherency (LPC) memory allows the host to access memory on an OpenCAPI device. When the P10 chip accesses memory addresses on the AFU, the Real Address on the PowerBus must hit a BAR in the PAU such as GPU-Memory BAR. The BAR defines the range of Real Addresses that represent AFU memory. The two existing OPAL calls, OPAL_NPU_MEM_ALLOC and OPAL_NPU_MEM_RELEASE are used to manage the AFU momory. Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-10-19pau: mmio invalidatesChristophe Lombard2-0/+39
The remaining translation mode: OpenCAPI 5.0 with TLBI/SLBI Snooping, is not used due to performance problems caused by the mismatch between the ERAT and Bloom Filter sizes. When the Address Translation Mode requires TLB and SLB Invalidate operations to be initiated using MMIO registers, a set of registers like the following is used: • XTS MMIO ATSD0 LPARID register • XTS MMIO ATSD0 AVA register • XTS MMIO ATSD0 launch register, write access initiates a shoot down • XTS MMIO ATSD0 status register Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-10-19pau: update current opal call functionsChristophe Lombard2-0/+165
Update the content of three current OPAL API calls to support PAU. - OPAL_NPU_SPA_SETUP The Shared Process Area (SPA) is a table containing one entry (a "Process Element") per memory context which can be accessed by the OpenCAPI device. - OPAL_NPU_SPA_CLEAR_CACHE The PAU keeps a cache of recently accessed memory contexts. When a Process Element is removed from the SPA, the cache for the link must be cleared. - OPAL_NPU_TL_SET The Transaction Layer specification defines several templates for messages to be exchanged on the link. During link setup, the host and device must negotiate what templates are supported on both sides and at what rates those messages can be sent. Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-10-19pau: link trainingChristophe Lombard1-0/+529
Add elementary functions to handle a phb complete, fundamental and hot resets. For the time being, specific creset and hreset are not supported. A complete fundamental reset is based on the following steps, in this order: - Place all bricks into Fence state - Disable BARs - Reset ODL to Power-on Values - Set the i2c reset pin in output mode - Initialize PHY Lanes - Deassert ODL reset - Clear the the i2c reset pin - Unfence bricks - Enable BARs - Enable ODL training mode Link training is also set up. Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-10-19pau: phy initChristophe Lombard2-1/+311
Follow the Procedure IO_INIT_RESET_PON as described in the P10 OPHY workbook document to reset and initialize the PHY lanes. The memory mapped SRAM (64 bit aligned) has to be used to configure the PHY, which is reachable the linked registers: address and data. The different links can be configured at the same time, that implies using a global lock to avoid conflicts. Authored-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-10-19pau: hmi scom dumpChristophe Lombard2-24/+47
This patch add a new function to dump PAU registers when a HMI has been raised and an OpenCAPI link has been hit by an error. For each register, the scom address and the register value are printed. The hmi.c has been redesigned in order to support the new PHB/PCIEX type (PAU OpenCapi). Now, the *npu* functions support NPU and PAU units of P8, P9 and P10 chips. Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-10-19pau: complete phb opsChristophe Lombard1-0/+137
Add more PHB interfaces: - to control pci error type in case of freeze. - add the addresses of the registers needed by the OS to handle translation failures. - to detect the fence state of a specific brick - to configure BDF (Bus Device Function) and PE (Partitionable Endpoint) for context identification. Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-10-19pau: enable interrupt on errorChristophe Lombard1-0/+157
The default action for the errors (unexpected errors on the opencapi link) reported in the PAU FIR2 registe is mostly set to system checkstop. This patch changes the default action of those errors so that the PAU will raise an interrupt instead. Interrupt information are logged so that the error can be debugged and linux can catch the event. Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-10-19pau: translation layer configurationChristophe Lombard1-0/+192
Next main part of the hypervisor PAU initialization. The P10 PAU supports two OpenCAPI links. The PAU provides various configuration selections for both of the OCAPI Link Transaction Layer functions (OTLs). These include a link enable, behavior controls, debug modes, and virtual channel credits to send to the AFU. The OTL Configuration 0, OTL Configuration 1, OTL Configuration 2, and TLX Credit Configuration registers are used to control these functions. This patch completes the PAU configuration following the sections 17.1.3.4 to 17.1.3.10.2 of the workbook document. Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-10-19pau: enabling opencapiChristophe Lombard1-0/+222
Enable OpenCAPI mode for each brick which are connected to be used in this mode. This is be done through 7 steps as described in the P10 OCAPI 5.0 Processing Unit Workbook document, section: 17.1.3.1 Enabling OpenCAPI. The following sequences must be performed: 1. Set Transport MUX controls to select OpenCAPI 2. Enable Clocks in XSL 3. Enable Clocks in MISC 4. Set NPCQ configuration 5. Enable XSL-XTS Interfaces 6. Enable State-machine allocation Enabling the NTL/GENID BARS allows to access to the MMIO registers. Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-10-19pau: create phbChristophe Lombard1-1/+233
Implement the necessary operations for the OpenCAPI PHB type and inform the device-tree properties associated. The OpenCapi PCI config Addr/Data registers are reachable through the Generation-ID Registers MMIO BARS. The Config Address and Data registers are located at the following offsets from the AFU Config BAR plus 320 KB. • Config Address for Brick 0 – Offset 0 • Config Data for Brick 0 – Offsets: ◦ 128 – 4-byte config register • Config Address for Brick 1 – Offset 256 • Config Data for Brick 1 – Offsets: ◦ 384 – 4-byte config register Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-10-19pau: assign barsChristophe Lombard2-8/+126
Configure early PAU Global MMIO BAR registers to allow PAU MMIO register accesses. This is done for each PAU. Enable the Powerbus interface is mandatory for MMIO accesses. For each OpenCAPI device, configure the bar registers to access to the AFU MMIO and to the AFU Config Addr/Data registers. AFU Config/Data registers = GENID_ADDR (from phy_map file) + 320K (= 0x50000) Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-10-19pau: introduce supportChristophe Lombard2-1/+225
OpenCapi for P10 is included in the P10 chip. This requires OCAPI capable PHYs, Datalink Layer Logic and Transaction Layer Logic to be included. The PHYs are the physical connection to the OCAPI interconnect. The Datalink Layer provides link training. The Transaction Layer executes the cache coherent and data movement commands on the P10 chip. The PAU provides the Transaction Layer functionality for the OCAPI link(s) on the P10 chip. The P10 PAU supports two OCAPI links. Six accelerator units PAUs are instantiated on the P10 chip for a total of twelve OCAPI links. This patch adds PAU opencapi structure for supporting OpenCapi5. hw/pau.c file contains main of PAU management functions. Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-10-19npu2: move opal apiChristophe Lombard2-35/+69
Move the OPAL entry points for npu2 opencapi to the common opal NPU file. This prepares us to add same entries for PAU opencapi in this common file. No functional change. Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-10-19AWAN simulator support for P10Ryan Grimm1-2/+5
This patch enables Skiboot to initialize and Linux to boot to user space on the AWAN core and chip models. We need the distinction between core and chip models because the core models do not have an XSCOM unit, CHIPTOD, nor RNG. The chip model does have them and they work. So, add a device_type property to the awan node to distinguish core from chip. Sample DTS are provided for the core and chip models in external/awan. Just like Mambo, we need to return in slw_init before trying to initialize SLW. Without an XSCOM unit in the device tree for the core model, the SLW code path eventually fails an assert due to lack of chips. This commit defines a QUIRK_AWAN where previously Mambo used QUIRK_MAMBO_CALLOUTS so now Mambo and AWAN core both work. Also, fix up chip quirks so the core model and chip model boot and initialize the appropriate units. Disable sreset and power management in a couple spots because the chip model does not support stop with EC=1 and enter_p9_pm_state spins in the branch-to-self after stop. Provide an external/awan/README.md with a high-level view of booting in the environment. Signed-off-by: Ryan Grimm <grimm@linux.ibm.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-10-19flash: AST BMC endian fixesNicholas Piggin1-3/+11
Fix endian for the 4-byte LPC copy similarly to other flash drivers. This allows flash to be detected on POWER8 AST BMC systems with a LE skiboot. Fix incorrect comments in those other drivers while we're here. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-10-19phb3: make endian-cleanNicholas Piggin1-158/+159
Convert phb3 dt construction and in-memory hardware tables to use explicit endian conversions. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-10-19Remove support for POWER8 DD1Nicholas Piggin2-379/+12
This significantly simplifies the SLW code. HILE is now always supported. Reviewed-by: Stewart Smith <stewart@flamingspork.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
generated by cgit v1.1 at 2024-06-29 01:25:26 +0000