| Age | Commit message (Collapse) | Author | Files | Lines |
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Added logic to handle cases where the Line Status Register (LSR)
reads 0xFF, which may indicate an error in reading the
register through LPC or the presence of multiple simultaneous UART errors.
previously, This false read of set bit lead to soft lock or hand in older
production systems.
In such scenarios, processing data read/write operations does
not make sense. The function now returns `false` to signal
the failure and halt further operations.
Signed-off-by: Abhishek Singh Tomar <abhishek@linux.ibm.com>
Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
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According to doc/opal-api/opal-console-read-write-1-2.rst, the length
argument of OPAL_CONSOLE_WRITE_BUFFER_SPACE is only used to return a
value. Indeed, the API is called twice in the kernel code, and __length
remains uninitialized in both cases. This can lead to a hang/softlock
issue in older hardware.
Eliminate the problematic comparison which uses the uninitialized value.
Fixes: 6bf21350da32 ("uart: Drop console write data if BMC becomes unresponsive")
Signed-off-by: Abhishek Singh Tomar <abhishek@linux.ibm.com>
Reviewed-by: Aditya Gupta <adityag@linux.ibm.com>
Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
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When BMC is in NTP mode, SET_SEL_TIME returns IPMI wrong state errors.
This better tracks and returns IPMI errors from OPAL_RTC_WRITE, which
prevents Linux from continuing to retry this non-transient failure.
Could the BMC be switched to non-NTP mode some time after the OS is up?
The host could see the OPAL_WRONG_STATE return and deal with this if
necessary.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
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The push-context operation is not defined if a context is already
valid, it should only be performed if the CAM is pulled. Add a check
to ensure the TIMA reset was performed properly before pushing a
context.
QEMU does not yet model the reset via PTER toggle correctly, so this
causes some noise in boot.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
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The LPC firmware memory space is 256MB in size, and it may select
up to 16 devices with the IDSEL field.
OPB addresses FW space as a 32-bit value with the top 4 bit selecting
the device and the bottom 28 addressing the FW memory space. Therefore
the top bits should ignored when calculating the offset into the FW
window.
Fix this by allowing lpc_opb_prepare() to adjust the address directly
and correctly mask it. Now there's no need to return opb_base to the
caller either, fold that in at the same time.
This bug could be observed with QEMU's PNOR implementation that placed
some of the PNOR in device 1, though that has been changed in QEMU 10.0.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
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Add validation of BT FIFO sizes against IPMI message allocations.
The BT interface capabilities command returns one less than the FIFO
size, so fix this off by one error in the sanity check.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
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On systems with redundant FSP, opal detects primary/backup FSPs.
However, it ends up considering Backup FSP as active_fsp and starts
mailbox communication with it. This causes opal to send IPL messages to
backup FSP instead of primary. Since primary FSP never receives IPL
messages from OPAL, it assumes that opal failed to boot and enters into
termination state.
The active_fsp is set during fsp_update_links_states() function which is
invoked during boot, through fsp_create_fsp(), as well as reset/reload,
through fsp_reinit_fsp(). During the boot, when 2 FSPs are detected by
opal, fsp_update_links_states() sets the last one as active_fsp which
may not be primary FSP.
Fix this issue by detecting/setting primary FSP as active_fsp during
opal boot.
Signed-off-by: Mahesh Salgaonkar <mahesh@linux.ibm.com>
Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
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Detect Power11 PVR and use P10 code path.
Signed-off-by: Mahesh Salgaonkar <mahesh@linux.ibm.com>
[adityag: Add Power11 chiptod device node]
[adityag: Fix the proc_gen checks in pir_to_thread_id and bmc sensor]
Signed-off-by: Aditya Gupta <adityag@linux.ibm.com>
Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
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P10 has a lower minimum timeout threshold than P9 (100usecs).
Some P10 SBE timers run about 6.7% slow, which must be a hardware or
firmware issue. Use the SBE timer health checking code to detect this
and compensate for it. Speeding up timers as a rule is dangerous because
early-expiry is a bug, howerver the core timer code checks expiry against
the CPU's timebase when running timers, and with the previous changes it
will schedule a new SBE timer for the remaining delay. So if this
adjustment speeds things up slightly too much, it won't cause bugs.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
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The SBE in P10 has a maximum expiry limit of just over 10s, so limit
SBE timers to 10s. If the desired timeout is longer than 10s,
additional SBE timers will be scheduled as the 10s timers are
serviced.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
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sbe_last_gen_stamp isn't a very clear name, so rename it to
sbe_current_timer_tb first of all. This is used to detect if
the timer should be programmed to get an earlier timeout.
One issue with it is that it is set *after* the SBE acks the
timer message, at which point the SBE could already have
started counting the timer. This means the SBE timer interrupt
could come in before that time, which is confusing and error
prone. Set the field at the point the timer is submitted to
the SBE.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
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These aren't "defaults", but really minimum advertised accurate timeouts.
Rename them and make them variables to accommodate changes for P10.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
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SBE timer messages are rate-limited so as not to flood the SBE. 2 timer
updates are permitted before the next timer interrupt. The problem with
this is that any subsequent sooner timers will not reprogram the
interrupt earlier so will be arbitrarily delayed.
Change this code to allow 3 updates, and have the 3rd update program
the SBE to the minimum expiry time, which gives rate-limiting without
compromising timer accuracy.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
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Disabling the SBE timer entirely is counter-productive: the SBE
interrupt can be delayed for a number of reasons including booting
or OS bugs, and there is no other timer to replace it. If the SBE
timer is detected to be lagging, increase polling rate until it
fires but keep it running.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
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When the SBE interrupt fires, clear the previous sbe_timer_target
and has_new_target variables, because the timer code will send us
an updated timer expiry after running check_timers().
This allows for example, a case where the SBE timer has fired too
early to reschedule the SBE timer again rather than leaving it to
be picked up by polling. SBE timer can fire early if the timer
exceeds its maximum timeout, or of the SBE timing is a little off.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
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SBE message acks should always apply to the first message in the list,
if the message list is empty this would be a bug, so print an error
message in that case.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
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Add a SBE health check when initialising the SBEs, which sends a timer
message and checks for the ack and timer expiry responses. This is
better than eventually finding a timer is not firing and shutting down
the SBE timer, it also tests SBEs on all chips in the system, not just
the primary.
This bypasses the queueing code to make things simpler, which is
okay because the SBEs are not up yet so no other messages are being
sent to the SBE.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
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The sequence number is a low level SBE hardware detail, so it can
be assigned later when the message is being sent to the SBE. This
allows SBE messages to be sent without queueing in special cases.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
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There appears to be no device-tree test for the P9 SBE presence like
there is for P8. The P9 device tree test looks for the "primary"
property, but this doesn't really test SBE presence because all chips
have an SBE. It just happens to work because mambo must not add that
property.
So add a platform quirk, and mark mambo and awan as not having SBE.
This is needed for a later change that runs a health check on every
SBE in the system.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
[arbab: Add #include <chip.h>]
Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
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Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
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The POWER10 init case is just a duplicate of POWER9 for now, so
consolidate it. Add an error message for unknown response type.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
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POWER10 addition accidentally changed a structure size by one byte.
Fixes: c8c36ada1d9a ("occ: Add POWER10 support")
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
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This test is always false due to a typo, which disables OCC
sensor and command functions. Not sure why compiler doesn't warn about
always true condition.
Fixes: c8c36ada1d9a ("occ: Add POWER10 support")
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
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Add a name string to LPC client irq sources.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
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QEMU has a bug where it loses the BT interrupt somewhere between BT
and XIVE when the OS boots.
For now, add a workaround QEMU quirk in the poller to try to kick
things along again.
SBE suffers the same problem but it has a poller that kicks the SBE and
gets it going again. Suspect the PSI interrupts may not be re-presented
after the OS re-initialises XIVE. This issue does not seem to appear on
real hardware.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
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Waiting for PCI reset is the most costly component of a QEMU boot,
mostly due to 1s delay between PERST deassert and device config
space access. These PCI hardware delays are not required with QEMU,
so skip them on that platform.
On a single-CPU QEMU powernv10 machine where PCI probing is not well
parallelised, this reduces skiboot boot time from 6.3s to 0.4s. This is
important for testing and CI.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
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Add endian annotations to NPU OPAL APIs, and fix warnings and bugs
reported by sparse.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
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On systems running BML we started noticing this in the skiboot log:
[ 409.088819302,3] XSCOM: write error gcid=0x0 pcb_addr=0x20000060 stat=0x4
[ 409.088823446,3] ELOG: Error getting buffer to log error
[ 409.088824806,3] XSCOM: Write failed, ret = -26
[ 409.088825797,3] IMC: error in xscom_write for pdbar
[ 0.468976][ T19] core_imc memory allocation for cpu 0 failed
[ 0.468993][ T1] IMC PMU core_imc Register failed
I tracked down that bad pcb_addr to this line in the code:
pdbar_addr = get_imc_scom_addr_for_quad(phys_core_id,
pdbar_scom_index[port_id]);
I found that pdbar_scom_index was not initialized because, like mambo, we don't
have the IMC catalog in memory. So, in imc_init we error out and never
initialize it in setup_imc_scoms.
This patch adds a chip quirk QUIRK_BML because it seems like a reasonable thing
to do and it's easy to put a BML {}; in the device tree like Mambo, Awan, etc.
It is tested on a Rainier and errors are gone and /sys/devices/core_imc shows
up as expected.
Signed-off-by: Ryan Grimm <grimm@linux.ibm.com>
Reviewed-By: Madhavan Srinivasan <maddy@linux.ibm.com>
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skiboot only supports POWER8 > DD1 now, all supported platforms
should use the new SPIRA-S/H structure.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
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The nest IMC (In Memory Collection) Performance Monitoring
Unit(PMU) node names are saved as "struct nest_pmus_struct"
in the "hw/imc.c" IMC code. Not all the IMC PMUs listed in
the device tree may be available. Nest IMC PMU names along with
their bit values is represented in imc availability vector.
This struct is used to remove the unavailable nodes by checking
this vector.
For power10, the imc_chip_avl_vector ie, imc availability vector
( which is a part of the IMC control block structure ), has
change in mapping of units and bit positions. Hence rename the
existing nest_pmus array to nest_pmus_p9 and add entry for power10
as nest_pmus_p10.
Also the avl_vector has another change in bit positions 11:34. These
bit positions tells the availability of Xlink/Alink/CAPI. There
are total 8 links and three bit field combination says which link
is available. Patch implements all these change to handle
nest_pmus_p10.
Signed-off-by: Athira Rajeev <atrajeev@linux.vnet.ibm.com>
Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
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The nest IMC (In Memory Collection) Performance Monitoring
Unit(PMU) node names are saved in nest_pmus[] array in the
"hw/imc.c" IMC code. Not all the IMC PMUs listed in the device
tree may be available. Nest IMC PMU names along with their
bit values is represented in imc availability vector.
The nest_pmus[] array is used to remove the unavailable nodes
by checking this vector.
To check node availability, code was using "dt_find_by_substr".
But since the node names have format like: "name@offset",
dt_find_by_name doesn't return the expected result. Fix this
by using dt_find_by_name_before_addr. Also, update the char array
to use correct node names.
Signed-off-by: Athira Rajeev <atrajeev@linux.vnet.ibm.com>
Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
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Enable the mctp binding over LPC bus interface and new wrappers to send
and receive PLDM messages over the mctp library.
PLDM is supported as a message type over MCTP. PLDM over MCTP binding
defines the format of PLDM over MCTP messages.
An MCTP Endpoint is the terminus for MCTP communication. A physical device
that supports MCTP may provide one or more MCTP Endpoints. Endpoints are
addressed using a logical address called the Endpoint ID, or EID. EIDs in
MCTP are analogous to IP Addresses in Internet Protocol networking.
The BMC EID default is 8.
First byte of the PLDM over MCTP Message Fields identifies the MCTP
message as carrying a PLDM message:
Message Type (7 bits) PLDM = 0x01 (000_0001b).
Reviewed-by: Abhishek Singh Tomar <abhishek@linux.ibm.com>
Signed-off-by: Christophe Lombard <clombard@linux.ibm.com>
Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
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The Management Component Transport Protocol (MCTP) defines a communication
model intended to facilitate communication.
This patch initialize MCTP binding over LPC Bus interface.
Several steps must be performed:
- Initialize the MCTP core (mctp_init()).
- Initialize a hardware binding as AST LPC mode host (mctp_astlpc_init()).
- Register the hardware binding with the core (mctp_register_bus()), using
a predefined EID (Host default is 9).
To transmit a MCTP message, mctp_message_tx() is used.
To receive a MCTP message, a callback need to be provided and registered
through mctp_set_rx_all().
For the transfer of MCTP messages, two basics components are used:
- A window of the LPC FW address space, where reads and writes are
forwarded to BMC memory.
- An interrupt mechanism using the KCS interface.
hw/ast-bmc/ast-mctp.c is compilated if the compiler flag CONFIG_PLDM is
set.
Reviewed-by: Abhishek Singh Tomar <abhishek@linux.ibm.com>
Signed-off-by: Christophe Lombard <clombard@linux.ibm.com>
Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
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Add new lpc helpers for doing a bulk io to firmware space.
Reviewed-by: Abhishek Singh Tomar <abhishek@linux.ibm.com>
Signed-off-by: Christophe Lombard <clombard@linux.ibm.com>
Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
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The define for PSIHB_XIVR was removed with P7 support.
Signed-off-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
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There is a QEMU model for ChipTOD (not yet upstream) that provides
enough to get through skiboot's sync sequence.
So run the chiptod init when running under QEMU, if it is being
provided in the device tree. If not, don't crash because the QEMU
patch has not been merged yet...
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
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This code hasn't been enabled, remove it.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
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Bring ipmi to a consistent state before booting a kernel by flushing
all outstanding messages. The OS may not start kicking the IPMI state
machine for some time.
For example, without this change, when booting in QEMU, the IPMI command
issued by ipmi_wdt_final_reset() to disable the watchdog is not sent to
the BMC before the OS boots, effectively leaving the watchdog enabled
until the OS begins to drive OPAL pollers.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: Stewart Smith <stewart@flamingspork.com>
Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
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Move all platforms using astbmc_init() to use astbmc_exit().
Move ipmi_set_boot_count() to astbmc_exit from ipmi_wdt_final_reset().
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
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free() asserts because local_alloc() doesn't allocate from the skiboot
heap region. Fix this by using local_free().
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
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The documented PEC recovery procedure is to clear the PEC FIR
registers when the ETU/PHB is in reset. However, any xscom access
targeting a PHB register while it is in reset will raise a new
error (PFIR bit 3), so it is possible to get out of reset and still
have a FIR register showing errors. It has been observed that the OCC,
through its 24x7 service, can do such a xscom access at boot time if
we end up in the CRESET path. So the current behavior of logging an
error is not desirable.
The recommendation from the logic designer is to keep the existing
mechanism to clear the FIR registers and add an extra step to clear
any new errors immediately after taking the ETU out of reset. That's
what this patch is doing.
Fixes: https://github.com/open-power/skiboot/issues/273
Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
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This patch improves readability just a tiny bit by using symbols, most
of them already existing, instead of values when accessing the PEC
registers.
No functional changes.
Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
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When looking for which interrupts are serviced by opal, we scan all
sources and query every single interrupt to know if it's for linux or
opal. An optimization was made so that if the source doesn't have an
'interrupt' op (=the handler) or an 'attributes' op (to do the
query), then we can skip the source. That's all good.
However, when xive was introduced, the 'irq_source' defining those ops
was wrapped in a 'xive_src' source which adds a level of indirection
for those 'attributes' and 'interrupt' ops. So the previous
optimization no longer works: the 'attributes' and 'interrupt' ops are
defined from the wrapper, but if we could look past the indirection,
we would realize they are not.
That is getting problematic for the rather large generic IPIs
source. We have 8 million such interrupts defined per chip on P10 and
because the above optimization is no longer kicking in, we are now
querying every single one of them to know if it is for opal. Real
hardware swallows it without much difficulty, but simulators
don't. Running qemu on my laptop, the full scan takes ~12 seconds per
chip!
This patch adds a callback for an interrupt source to report whether
it has opal interrupts. If the source doesn't define it, then we
fallback to looking at the 'interrupt' and 'attributes' ops, like
before, as it is still useful on P8. We can then define that new
callback on the xive sources, allowing to look past the indirection
level and skip scanning the source when appropriate.
Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
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There's no reason to skip 2 bits when printing the Notification Source
Register (NSR) of any thread context ring. So it's got to be a silly
mistake and we should shift by 56 bits and not 58 :-)
Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Reviewed-by: Dan Horák <dan@danny.cz>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
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Caught by CI in fedora-rawhide (GCC 12):
hw/fsp/fsp-codeupdate.c:116:26: error: '%s' directive argument is null [-Werror=format-overflow=]
116 | prlog(PR_NOTICE, "CUPD: IPL SIDE = %s\n", side);
To prevent this, explicitly print the value of ipl_side instead.
Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
Reviewed-by: Dan Horák <dan@danny.cz>
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Use a look up table to support the p9, p10dd1 and p10dd2 conversions.
Running on a Rainier:
> [ 268.267370706,6] CPU: P10 generation processor (max 4 threads/core)
> [ 268.267372501,7] CPU: Boot CPU PIR is 0x0460 PVR is 0x00801200
> [ 268.284420384,5] CHIP: Chip ID 0000 type: P10 DD2.02
> [ 268.284464084,5] CHIP: Chip ID 0002 type: P10 DD2.02
> [ 268.284500468,5] CHIP: Chip ID 0004 type: P10 DD2.02
> [ 268.284538166,5] CHIP: Chip ID 0006 type: P10 DD2.02
> [ 268.286317879,5] PLAT: Detected Rainier platform
Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Dan Horák <dan@danny.cz>
Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
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In preparation for adding p10 logic. No functional change.
Reviewed-by: Dan Horák <dan@danny.cz>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
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Resolves : the warray bounds warning during compilation
/build/libc/include/string.h:34:16: warning: '__builtin_memset' offset [0, 2097151] is out of the bounds [0, 0] [-Warray-bounds]
34 | #define memset __builtin_memset
hw/fsp/fsp.c:1855:9: note: in expansion of macro 'memset'
1855 | memset(fsp_tce_table, 0, PSI_TCE_TABLE_SIZE);
use volatile pointer to avoid optimization introduced with gcc-11 on constant
address assignment to pointer.
Signed-off-by: Abhishek Singh Tomar <abhishek@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
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Make the P8 NPU code depend on CONFIG_P8. This requires converting
a low level function to a no-op because the HMI NPU handling is not
so cleanly layered.
This saves an extra 6kb of skiboot.lid.xz.
Reviewed-by: Dan Horák <dan@danny.cz>
Signed-off-by: Stewart Smith <stewart@flamingspork.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
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Convert VAS and NX to use the hwprobe facility for init.
Reviewed-by: Dan Horák <dan@danny.cz>
[npiggin: remove imc_init because it moved later in boot (fbcbd4e47c)]
Signed-off-by: Stewart Smith <stewart@flamingspork.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
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