npu3: Initialize NPU3_SNP_MISC_CFG0

Enable powerbus snooping here, or else MMIO to any NTL/NDL registers
will cause a checkstop.

This was not an issue in Simics simulation, but discovered rather
quickly during bringup on a real Axone chip.

Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
Reviewed-by: Christophe Lombard <clombard@linux.vnet.ibm.com>
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>

1 files changed, 7 insertions, 0 deletions

diff --git a/hw/npu3.c b/hw/npu3.c
index ea687f4..4d396b0 100644
--- a/hw/npu3.c
+++ b/hw/npu3.c
@@ -309,6 +309,13 @@ static void npu3_misc_config(struct npu3 *npu)
 	val = SETFIELD(NPU3_MCP_MISC_CFG0_OCAPI_MODE, val, ~typemap);
 	npu3_write(npu, reg, val);
 
+	reg = NPU3_SNP_MISC_CFG0;
+	val = npu3_read(npu, reg);
+	val |= NPU3_SNP_MISC_CFG0_ENABLE_PBUS;
+	val = SETFIELD(NPU3_SNP_MISC_CFG0_NVLINK_MODE, val, typemap);
+	val = SETFIELD(NPU3_SNP_MISC_CFG0_OCAPI_MODE, val, ~typemap);
+	npu3_write(npu, reg, val);
+
 	reg = NPU3_CTL_MISC_CFG2;
 	val = npu3_read(npu, reg);
 	val = SETFIELD(NPU3_CTL_MISC_CFG2_NVLINK_MODE, val, typemap);