aboutsummaryrefslogtreecommitdiff
path: root/hw/ast-bmc
AgeCommit message (Collapse)AuthorFilesLines
2023-09-12core/pldm: PLDM over MCTP BindingChristophe Lombard1-0/+18
Enable the mctp binding over LPC bus interface and new wrappers to send and receive PLDM messages over the mctp library. PLDM is supported as a message type over MCTP. PLDM over MCTP binding defines the format of PLDM over MCTP messages. An MCTP Endpoint is the terminus for MCTP communication. A physical device that supports MCTP may provide one or more MCTP Endpoints. Endpoints are addressed using a logical address called the Endpoint ID, or EID. EIDs in MCTP are analogous to IP Addresses in Internet Protocol networking. The BMC EID default is 8. First byte of the PLDM over MCTP Message Fields identifies the MCTP message as carrying a PLDM message: Message Type (7 bits) PLDM = 0x01 (000_0001b). Reviewed-by: Abhishek Singh Tomar <abhishek@linux.ibm.com> Signed-off-by: Christophe Lombard <clombard@linux.ibm.com> Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
2023-09-12hw/ast-bmc: Initialize ast lpc mctp bindingChristophe Lombard2-0/+371
The Management Component Transport Protocol (MCTP) defines a communication model intended to facilitate communication. This patch initialize MCTP binding over LPC Bus interface. Several steps must be performed: - Initialize the MCTP core (mctp_init()). - Initialize a hardware binding as AST LPC mode host (mctp_astlpc_init()). - Register the hardware binding with the core (mctp_register_bus()), using a predefined EID (Host default is 9). To transmit a MCTP message, mctp_message_tx() is used. To receive a MCTP message, a callback need to be provided and registered through mctp_set_rx_all(). For the transfer of MCTP messages, two basics components are used: - A window of the LPC FW address space, where reads and writes are forwarded to BMC memory. - An interrupt mechanism using the KCS interface. hw/ast-bmc/ast-mctp.c is compilated if the compiler flag CONFIG_PLDM is set. Reviewed-by: Abhishek Singh Tomar <abhishek@linux.ibm.com> Signed-off-by: Christophe Lombard <clombard@linux.ibm.com> Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
2021-10-19flash: AST BMC endian fixesNicholas Piggin1-3/+11
Fix endian for the 4-byte LPC copy similarly to other flash drivers. This allows flash to be detected on POWER8 AST BMC systems with a LE skiboot. Fix incorrect comments in those other drivers while we're here. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2020-03-12Re-license IBM written files as Apache 2.0 OR GPLv2+Stewart Smith3-3/+3
SPDX makes it a simpler diff. I have audited the commit history of each file to ensure that they are exclusively authored by IBM and thus we have the right to relicense. The motivation behind this is twofold: 1) We want to enable experiments with coreboot, which is GPLv2 licensed 2) An upcoming firmware component wants to incorporate code from skiboot and code from the Linux kernel, which is GPLv2 licensed. I have gone through the IBM internal way of gaining approval for this. The following files are not exclusively authored by IBM, so are *not* included in this update (I will be seeking approval from contributors): core/direct-controls.c core/flash.c core/pcie-slot.c external/common/arch_flash_unknown.c external/common/rules.mk external/gard/Makefile external/gard/rules.mk external/opal-prd/Makefile external/pflash/Makefile external/xscom-utils/Makefile hdata/vpd.c hw/dts.c hw/ipmi/ipmi-watchdog.c hw/phb4.c include/cpu.h include/phb4.h include/platform.h libflash/libffs.c libstb/mbedtls/sha512.c libstb/mbedtls/sha512.h platforms/astbmc/barreleye.c platforms/astbmc/garrison.c platforms/astbmc/mihawk.c platforms/astbmc/nicole.c platforms/astbmc/p8dnu.c platforms/astbmc/p8dtu.c platforms/astbmc/p9dsu.c platforms/astbmc/vesnin.c platforms/rhesus/ec/config.h platforms/rhesus/ec/gpio.h platforms/rhesus/gpio.c platforms/rhesus/rhesus.c platforms/astbmc/talos.c platforms/astbmc/romulus.c Signed-off-by: Stewart Smith <stewart@linux.ibm.com> [oliver: fixed up the drift] Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-12-16add more sparse endian annotationsNicholas Piggin1-2/+3
This fixes quite a few sparse endian annotations across the tree. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-07-26SPDX-ify all skiboot codeStewart Smith3-30/+7
Use Software Package Data Exchange (SPDX) to indicate license for each file that is unique to skiboot. At the same time, ensure the (C) who and years are correct. See https://spdx.org/ Signed-off-by: Stewart Smith <stewart@linux.ibm.com> [oliver: Added a few missing files] Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-02-25astbmc: Try IPMI HIOMAP for P8 (again)Andrew Jeffery1-1/+6
The HIOMAP protocol was developed after the release of P8 in preparation for P9. As a consequence P9 always uses it, but it has rarely been enabled for P8. P8DTU has recently added IPMI HIOMAP support to its BMC firmware, so enable its use in skiboot with P8 machines. Doing so requires some rework to ensure fallback works correctly as in the past the fallback was to mbox, which will only work for P9. Tested on Garrison, Palmetto without HIOMAP, Palmetto with HIOMAP, and Witherspoon. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
2019-02-25ast-io: Rework ast_sio_is_enabled() test sequenceAndrew Jeffery1-9/+30
The postcondition of probing with a lock sequence is easier to make correct than with unlock. The original implementation left SuperIO locked after execution which broke an assumption of some callers. Tested on Garrison, Palmetto without HIOMAP, Palmetto with HIOMAP and Witherspoon. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
2019-02-10Revert "astbmc: Try IPMI HIOMAP for P8"Joel Stanley1-6/+1
This reverts commit bd9839684d482417e8c60449592f4308e9a91dac as it broke booting on P8 systems, including Garrison (AMI BMC), Firestone (AMI BMC) and QEMU (BMC simulator). Issue https://github.com/open-power/skiboot/issues/217 tracks the failure. The P8 IPMI HIOMAP feature can be re-enabled once this issue is resolved. Reported-by: Sam Mendoza-Jonas <sam@mendozajonas.com> Reported-by: Sam Mendoza-Jonas <sam@mendozajonas.com> Signed-off-by: Joel Stanley <joel@jms.id.au> Acked-by: Sam Mendoza-Jonas <sam@mendozajonas.com> Acked-by: Sam Mendoza-Jonas <sam@mendozajonas.com> Tested-by: Alexey Kardashevskiy <aik@ozlabs.ru> Acked-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
2019-01-18astbmc: Try IPMI HIOMAP for P8Andrew Jeffery1-1/+6
The HIOMAP protocol was developed after the release of P8 in preparation for P9. As a consequence P9 always uses it, but it has rarely been enabled for P8. P8DTU has recently added IPMI HIOMAP support to its BMC firmware, so enable its use in skiboot with P8 machines. Doing so requires some rework to ensure fallback works correctly as in the past the fallback was to mbox, which will only work for P9. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
2018-10-11astbmc: Fail SFC init if SIO is unavailableAndrew Jeffery1-0/+3
If SuperIO is unavailable then the driver cannot perform accesses on which it currently depends. Test for SuperIO availability during initialsation and bail out immediately if it is absent. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
2018-10-11platform: Restructure bmc_platform typeAndrew Jeffery1-1/+1
Segregate the BMC platform configuration into hardware and software components. This allows population of platform default values for hardware configuration that may no-longer be accessible by the host. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> [stewart: fixup pci-quirk unit test] Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
2018-10-11astbmc: Use LPC probe calls to determine SIO presenceAndrew Jeffery1-20/+10
Avoid the probabilistic approach and use a deterministic one instead. The probe calls use a slow, synchronous method to capture the the state of the target device, so it is used sparingly (only on first access). Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
2018-10-11astbmc: Remove coordinated isolation supportAndrew Jeffery1-56/+0
Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
2018-10-11astbmc: Prefer ipmi-hiomap for PNOR accessAndrew Jeffery1-3/+7
If the IPMI command is not available, fall back to the mailbox interface. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> [stewart: fix up mbox test] Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
2018-08-13ast-io: Use bmc_sio_{get, put}() where requiredAndrew Jeffery1-1/+7
Booting the host with a particular BMC configuration could lead to the following error appearing in the OPAL msglog: [ 71.470748378,3] PLAT: AST IO initialisation failed! Wrap access to BMC_SIO_PLAT_FLAGS in bmc_sio_get()/bmc_sio_put() in order to unlock and relock the SuperIO controller as required and avoid the failure. Fixes: ebc8524a3a45 ("ast-io: Rework setup/tear-down of communication with the BMC") Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
2018-07-18Fixup pflash build for ast refactorStewart Smith1-1/+9
Fixes: 5b1bc2ffe791ae94361d86b2ae063ee543bf2df5 Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
2018-07-17lpc: Silence LPC SYNC no-response error when necessaryAndrew Jeffery1-0/+45
Add the ability to silence particular errors from the LPC bus when they can be expected, particularly: LPC[000]: Got SYNC no-response error. Error address reg: 0xd001002f This is necessary on platform exit on some astbmc machines to avoid unnecessary noise in the msglog. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
2018-07-17ast-io: Rework setup/tear-down of communication with the BMCAndrew Jeffery1-2/+61
It's possible for the platform to configure the BMC with SuperIO access disabled. Rework the interfaces to report failures if SuperIO is not enabled, and clean up once we're finished. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
2018-07-17ast-bmc: Rename LPC FW cycle helpersAndrew Jeffery1-2/+2
Introduce some consistency for readability and make the names better reflect the nature of the tests. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
2018-07-17ast-bmc: Move copy routines to ast-sf-ctrlAndrew Jeffery2-94/+94
The only user was hw/ast-bmc/ast-sf-ctrl.c, and for accessing flash the copy routines require knowledge of the PNOR LPC offset. For systems using MBOX the ast-sf-ctrl implementation is unused, so move the offset initialisation out of the common code-path and the copy routines to the place where they are necessary. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
2018-06-18astbmc: Enable mbox depending on scratch regJoel Stanley1-0/+14
P8 boxes can opt in for mbox pnor support if they set the scratch register bit to indicate it is supported. Signed-off-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
2018-06-18ast-bmc: Document BMC scratch registerJoel Stanley1-0/+20
ASPEED BMCs use SIO register 0x29 to configure host firmwrae settings. This documents those setings as currently used by Hostboot in [1]. Despite the naming, these settings are relevant for ast2500 systems as well. [1] src/usr/initservice/bootconfig/bootconfig_ast2400.H Signed-off-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
2018-02-28build: use thin archives rather than incremental linkingNicholas Piggin1-1/+1
This changes to build system to use thin archives rather than incremental linking for built-in.o, similar to recent change to Linux. built-in.o is renamed to built-in.a, and is created as a thin archive with no index, for speed and size. All built-in.a are aggregated into a skiboot.tmp.a which is a thin archive built with an index, making it suitable or linking. This is input into the final link. The advantags of build size and linker code placement flexibility are not as great with skiboot as a bigger project like Linux, but it's a conceptually better way to build, and is more compatible with link time optimisation in toolchains which might be interesting for skiboot particularly for size reductions. Size of build tree before this patch is 34.4MB, afterwards 23.1MB. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-02-23astbmc/pnor: Use mbox-flash for flash accessesCyril Bur1-0/+6
If the BMC is MBOX protocol aware, request flash reads/writes over the MBOX regs. This inits the blocklevel for pnor access with mbox-flash. Signed-off-by: Cyril Bur <cyril.bur@au1.ibm.com> Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-02-23ast-bmc: Use the mbox driverCyril Bur1-0/+19
The mbox registers are accessed via superIO, these need to be initialised. The mbox device node won't be present in the device tree hostboot passes us, so fixup the device tree. Signed-off-by: Cyril Bur <cyril.bur@au1.ibm.com> Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2016-09-15libflash: add 128MB MX66L1G45G partJoel Stanley1-0/+1
Signed-off-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2015-12-14libflash: fix 4bytes address enablement on BMC SPI flashCédric Le Goater1-1/+1
commit e25f3f3559d9 ("libflash: enable 4b mode on BMC SPI flash") added a setting for 4byte addresses on the BMC SPI flash when needed. This setting should be only done for the BMC flash, which is not the case in the current code. This patch fixes it. Signed-off-by: Cédric Le Goater <clg@fr.ibm.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2015-11-26libflash: enable 4b mode on BMC SPI flashJoel Stanley1-1/+9
We already support larger parts on the host flash, but the BMC has always had a 16MB part, so we did not need to enable the 4b addressing mode. This enables the 4b addressing mode when the flash is larger than 16MB. Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Cédric Le Goater <clg@fr.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2015-08-26Fix spelling mistakesStewart Smith1-2/+2
See https://github.com/lucasdemarchi/codespel Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2015-07-07libflash: Add support for Macronix 128Mb flash chipsJeremy Kerr1-0/+1
Fun-sized version of the MXxxL25635F. Signed-off-by: Jeremy Kerr <jk@ozlabs.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2015-03-26memboot: Add a memboot flash backendAlistair Popple2-15/+104
memboot uses bmc system memory instead of a real flash chip. This patch adds a flash backend for bmc system memory to allow use of the memboot tool (in external/memboot) to boot the system. Signed-off-by: Alistair Popple <alistair@popple.id.au> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2014-10-30libflash: Update from pflash-0.8.6Benjamin Herrenschmidt1-29/+77
Improve calibration and use safer timings for commands. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2014-10-15hw/ast: Print something decent for PNOR LPC offsetBenjamin Herrenschmidt1-1/+1
Print the actual offset rather than the register content and use PR_DEBUG log level Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2014-10-15libflash: Sync with pflash 0.8.3Benjamin Herrenschmidt1-83/+469
Fixes 64MB chip support, improve Macronix settings, add Micron chip support, etc... Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2014-10-15hw/ast: Make PNOR offset on LPC a variableBenjamin Herrenschmidt1-8/+14
Read the configuration from the BMC in order to be compatible with different size flash chips. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2014-10-08ast/io: Fix a number of issues with SuperIO accessBenjamin Herrenschmidt1-56/+74
The code to access AST registers via the iLPC->AHB bridge was very fragile and relied on the SIO to be kept unlocked with the right device selected. This got broken when adding the new UART configuration among other things. Rework this to create a pair of get/put() helpers to use to access a given SIO device, which take care of doing the appropriate device selection when needed and also take/release the SIO spinlock. This fixes Flash/NVRAM setup which got broken along the way and also makes the fixup for the VUART interrupts actually work. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2014-10-05plat/palmetto: Fix SIO UART vs UART setup and iBT setupBenjamin Herrenschmidt1-3/+107
The AMI images use the virtual UART, not the SIO UART, so configuring the SIO the way we do is incorrect. Additionally, they don't configure the interrupts properly (bad polarity for VUART and bad number for iBT). This reworks the inits to fix that up: - All SIO interrupts are set to level low - Check if VUART is enabled. If yes, configure and use it (and disable SIO UART which hostboot might have left enabled). - Else, reconfigure VUART LPC address and IRQ properly - Configure iBT LPC address and IRQ properly Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2014-07-02Initial commit of Open Source releaseBenjamin Herrenschmidt3-0/+741
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
generated by cgit v1.1 at 2024-07-17 02:57:34 +0000