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| author | Cédric Le Goater <clg@kaod.org> | 2021-08-04 12:51:14 +0530 |
|---|---|---|
| committer | Vasant Hegde <hegdevasant@linux.vnet.ibm.com> | 2021-08-06 12:27:28 +0530 |
| commit | 2a7e3d203496a016cc90ce91eeb2c4e680ebd1d2 (patch) | |
| tree | 3fa67869f50b982930ed0711a83aa2c16f1ef246 /include/phb4-regs.h | |
| parent | 5b2d7c79a2049c1bedfaa8a9dfa19880f980b2ef (diff) | |
| download | skiboot-2a7e3d203496a016cc90ce91eeb2c4e680ebd1d2.zip skiboot-2a7e3d203496a016cc90ce91eeb2c4e680ebd1d2.tar.gz skiboot-2a7e3d203496a016cc90ce91eeb2c4e680ebd1d2.tar.bz2 | |
hw/phb5: Add support for 'Address-Based Interrupt Trigger' mode
The PHB5 introduces a new Address-Based Interrupt mode which extends
the notification offloading to the ESB pages. When ABT is activated,
the PHB maps the interrupt source number into the interrupt command
address. The PHB triggers the interrupt using directly the IC ESB page
of the interrupt number and does not use the notify page of the IC
anymore.
The PHB interrrupt configuration under ABT is a little different. The
'Interrupt Notify Base Address' register points to the base address of
the IC ESB pages and not to the notify page of the IC anymore as on
P9. The 'Interrupt Notify Base Index' register is unused.
This should improve overall performance. The P10 IC can handle higher
interrupt rates compared to P9 and the PHB latency should be improved
under ABT. Debug is easier as the interrupt number is now exposed on
the PowerBUS.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
[FB: port to phb4.c]
Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
Diffstat (limited to 'include/phb4-regs.h')
| -rw-r--r-- | include/phb4-regs.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/include/phb4-regs.h b/include/phb4-regs.h index 1395228..99633e1 100644 --- a/include/phb4-regs.h +++ b/include/phb4-regs.h @@ -97,11 +97,13 @@ #define PHB_PAPR_ERR_INJ_MASK_MMIO PPC_BITMASK(16,63) #define PHB_ETU_ERR_SUMMARY 0x2c8 #define PHB_INT_NOTIFY_ADDR 0x300 +#define PHB_INT_NOTIFY_ADDR_64K PPC_BIT(1) /* PHB5 */ #define PHB_INT_NOTIFY_INDEX 0x308 #define PHB_VERSION 0x800 #define PHB_CTRLR 0x810 #define PHB_CTRLR_IRQ_PQ_DISABLE PPC_BIT(9) /* PHB5 */ +#define PHB_CTRLR_IRQ_ABT_MODE PPC_BIT(10) /* PHB5 */ #define PHB_CTRLR_IRQ_PGSZ_64K PPC_BIT(11) #define PHB_CTRLR_IRQ_STORE_EOI PPC_BIT(12) #define PHB_CTRLR_MMIO_RD_STRICT PPC_BIT(13) |