diff options
| author | Cédric Le Goater <clg@kaod.org> | 2021-08-04 12:51:13 +0530 |
|---|---|---|
| committer | Vasant Hegde <hegdevasant@linux.vnet.ibm.com> | 2021-08-06 12:26:59 +0530 |
| commit | 5b2d7c79a2049c1bedfaa8a9dfa19880f980b2ef (patch) | |
| tree | 0fa7a5a85530ec4435a42409bb870a30dffc7c64 /include/phb4-regs.h | |
| parent | 99041844eedca00bfedbd6181e3d4353d6e98a1d (diff) | |
| download | skiboot-5b2d7c79a2049c1bedfaa8a9dfa19880f980b2ef.zip skiboot-5b2d7c79a2049c1bedfaa8a9dfa19880f980b2ef.tar.gz skiboot-5b2d7c79a2049c1bedfaa8a9dfa19880f980b2ef.tar.bz2 | |
hw/phb5: Add support for PQ offloading
The POWER9 DD2.0 introduced a StoreEOI operation which had benefits
over the LoadEOI operation : less latency and improved performance for
interrupt handling. Because of load vs. store ordering issues in some
cases, it had to be deactivates. The POWER10 processor has a set
of new features in the XIVE2 and the PHB5 controllers to address this
problem.
At the interrupt controller level, XIVE2 adds a new load offset to the
ESB page which offers the capability to order loads after stores. It
should be enforced by the OS when doing loads if StoreEOI is to be
used.
But this is not enough. The firmware should also carefully configure
the PHB interrupt sources to make sure that operations on the PQ state
bits of a source are routed to a single logic unit : the XIVE2 IC.
The PHB5 introduces a new configuration PQ disable (bit 9) bit for
this purpose.
It disables the check of the PQ state bits when processing new MSI
interrupts. When set, the PHB ignores its local PQ state bits and
forwards unconditionally any MSI trigger to the XIVE2 interrupt
controller. The XIVE2 IC knows from the trigger message that the PQ
bits have not been checked and performs the check using the local PQ
bits. This configuration bit only applies to MSIs and LSIs are still
checked on the PHB to handle the assertion level.
This requires a new XIVE interface to register a HW interrupt source
using the IC ESB pages of the allocated HW interrupt numbers, and not
the ESB pages of the HW source. This is what this change proposes for
MSIs, LSI still being handled the old way.
PQ disable is a requirement for StoreEOI.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
[FB: port to phb4.c]
Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
Diffstat (limited to 'include/phb4-regs.h')
| -rw-r--r-- | include/phb4-regs.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/phb4-regs.h b/include/phb4-regs.h index 03b53ae..1395228 100644 --- a/include/phb4-regs.h +++ b/include/phb4-regs.h @@ -101,6 +101,7 @@ #define PHB_VERSION 0x800 #define PHB_CTRLR 0x810 +#define PHB_CTRLR_IRQ_PQ_DISABLE PPC_BIT(9) /* PHB5 */ #define PHB_CTRLR_IRQ_PGSZ_64K PPC_BIT(11) #define PHB_CTRLR_IRQ_STORE_EOI PPC_BIT(12) #define PHB_CTRLR_MMIO_RD_STRICT PPC_BIT(13) |