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| author | Frederic Barrat <fbarrat@linux.ibm.com> | 2021-08-04 12:51:31 +0530 |
|---|---|---|
| committer | Vasant Hegde <hegdevasant@linux.vnet.ibm.com> | 2021-08-06 12:30:20 +0530 |
| commit | 1622cc78e7a4ba1c7766e20ffaa2b3a40d6b5f1e (patch) | |
| tree | 7d5d209d7a21096c80ec7f1ff9c3714cd536dd2b /include/phb4-regs.h | |
| parent | 6af8ac2e00cddcdbdf673b3ea3ead9453c5445ba (diff) | |
| download | skiboot-1622cc78e7a4ba1c7766e20ffaa2b3a40d6b5f1e.zip skiboot-1622cc78e7a4ba1c7766e20ffaa2b3a40d6b5f1e.tar.gz skiboot-1622cc78e7a4ba1c7766e20ffaa2b3a40d6b5f1e.tar.bz2 | |
phb4: Cleanup PEC config discovery in CAPI mode
Small cleanup when reading the PEC config when setting up CAPI, in
preparation for P10. Scom addresses vary between P9 and P10 and we'll
be accessing more than one PCI chiplet. No functional change.
Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
Diffstat (limited to 'include/phb4-regs.h')
| -rw-r--r-- | include/phb4-regs.h | 10 |
1 files changed, 7 insertions, 3 deletions
diff --git a/include/phb4-regs.h b/include/phb4-regs.h index 85d2cf2..b4a94c0 100644 --- a/include/phb4-regs.h +++ b/include/phb4-regs.h @@ -385,9 +385,13 @@ /* PCI Chiplet Config Register */ -#define XPEC_PCI2_CPLT_CONF1 0x000000000F000009ULL -#define XPEC_PCI2_IOVALID_MASK PPC_BITMASK(4, 6) -#define XPEC_PCI2_IOVALID_X16 PPC_BIT(4) +#define XPEC_PCI_CPLT_OFFSET 0x1000000ULL +#define XPEC_P9_PCI_CPLT_CONF1 0x000000000D000009ULL +#define XPEC_P9_PCI_IOVALID_MASK PPC_BITMASK(4, 6) +#define XPEC_P9_PCI_IOVALID_X16 PPC_BIT(4) +#define XPEC_P9_PCI_LANE_CFG PPC_BITMASK(10, 11) +#define XPEC_P10_PCI_CPLT_CONF1 0x0000000008000009ULL +#define XPEC_P10_PCI_LANE_CFG PPC_BITMASK(0, 1) /* * IODA3 on-chip tables |