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| author | Frederic Barrat <fbarrat@linux.ibm.com> | 2019-03-12 21:35:10 +0100 |
|---|---|---|
| committer | Stewart Smith <stewart@linux.ibm.com> | 2019-03-13 21:55:18 -0500 |
| commit | e621b7b6795163d9f429d28fb120736fa4fad042 (patch) | |
| tree | a5a65885c60908c58ae57465f1ccae151c3f6fb5 /include/npu2-regs.h | |
| parent | 536c8fbf932d6a790f95cb8cf39dacf4a2de06cb (diff) | |
| download | skiboot-e621b7b6795163d9f429d28fb120736fa4fad042.zip skiboot-e621b7b6795163d9f429d28fb120736fa4fad042.tar.gz skiboot-e621b7b6795163d9f429d28fb120736fa4fad042.tar.bz2 | |
npu2-opencapi: Setup perf counters to detect CRC errors
It's possible to set up performance counters for the PLL to detect
various conditions for the links in nvlink or opencapi mode. Since
those counters are currently unused, let's configure them when an obus
is in opencapi mode to detect CRC errors on the link. Each link has
two counters:
- CRC error detected by the host
- CRC error detected by the DLx (NAK received by the host)
We also dump the counters shortly after the link trains, but they can
be read multiple times through cronus, pdbg or linux. The counters are
configured to be reset after each read.
Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com>
Reviewed-by: Christophe Lombard <clombard@linux.vnet.ibm.com>
Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
Diffstat (limited to 'include/npu2-regs.h')
| -rw-r--r-- | include/npu2-regs.h | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/include/npu2-regs.h b/include/npu2-regs.h index 5190aeb..ca31109 100644 --- a/include/npu2-regs.h +++ b/include/npu2-regs.h @@ -725,6 +725,23 @@ void npu2_scom_write(uint64_t gcid, uint64_t scom_base, #define PU_IOE_PB_FP_CFG_FP1_FMR_DISABLE PPC_BIT(52) #define PU_IOE_PB_FP_CFG_FP1_PRS_DISABLE PPC_BIT(57) +#define OB_DLL_PERF_MONITOR_CONFIG(brick_index) \ + (0x901081C + ((brick_index - 2) >> 1) * 0x3000000) +#define OB_DLL_PERF_MONITOR_CONFIG_ENABLE PPC_BITMASK(0, 1) +#define OB_DLL_PERF_MONITOR_CONFIG_LINK0 0b10 +#define OB_DLL_PERF_MONITOR_CONFIG_LINK1 0b01 +#define OB_DLL_PERF_MONITOR_CONFIG_SIZE PPC_BITMASK(16, 23) +#define OB_DLL_PERF_MONITOR_CONFIG_SIZE16 0xFF +#define OB_DLL_PERF_MONITOR_SELECT(brick_index) \ + (0x901081D + ((brick_index - 2) >> 1) * 0x3000000) +#define OB_DLL_PERF_MONITOR_SELECT_COUNTER PPC_BITMASK(0, 7) +#define OB_DLL_PERF_MONITOR_SELECT_CRC_ODL 0x44 +#define OB_DLL_PERF_MONITOR_SELECT_CRC_DLX 0x45 +#define OB_DLL_PERF_COUNTER0(brick_index) \ + (0x901081E + ((brick_index - 2) >> 1) * 0x3000000) +#define OB_DLL_PERF_COUNTER0_VAL PPC_BITMASK(0, 31) + + #define OB_ODL_OFFSET(brick_index) \ ((((brick_index - 2) >> 1) * 0x3000000) + ((brick_index == 3 || brick_index == 4) ? 1 : 0)) |