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| author | Frederic Barrat <fbarrat@linux.ibm.com> | 2019-03-12 21:35:09 +0100 |
|---|---|---|
| committer | Stewart Smith <stewart@linux.ibm.com> | 2019-03-13 21:55:18 -0500 |
| commit | 536c8fbf932d6a790f95cb8cf39dacf4a2de06cb (patch) | |
| tree | 2e6345c57b32fbf70f3ab63ec993e2e36087a97e /include/npu2-regs.h | |
| parent | 261ca8e779e5138869a45f174caa49be6a274501 (diff) | |
| download | skiboot-536c8fbf932d6a790f95cb8cf39dacf4a2de06cb.zip skiboot-536c8fbf932d6a790f95cb8cf39dacf4a2de06cb.tar.gz skiboot-536c8fbf932d6a790f95cb8cf39dacf4a2de06cb.tar.bz2 | |
npu2-opencapi: Rework ODL register access
ODL registers used to control the opencapi link state have an address
built on a base address and an offset for each brick which can be
computed instead of hard-coded individually for each brick.
Rework how we access the ODL registers, to avoid repeating switch
statements all over the place.
Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com>
Reviewed-by: Christophe Lombard <clombard@linux.vnet.ibm.com>
Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
Diffstat (limited to 'include/npu2-regs.h')
| -rw-r--r-- | include/npu2-regs.h | 30 |
1 files changed, 11 insertions, 19 deletions
diff --git a/include/npu2-regs.h b/include/npu2-regs.h index 38087aa..5190aeb 100644 --- a/include/npu2-regs.h +++ b/include/npu2-regs.h @@ -725,10 +725,11 @@ void npu2_scom_write(uint64_t gcid, uint64_t scom_base, #define PU_IOE_PB_FP_CFG_FP1_FMR_DISABLE PPC_BIT(52) #define PU_IOE_PB_FP_CFG_FP1_PRS_DISABLE PPC_BIT(57) -#define OB0_ODL0_CONFIG 0x901082A -#define OB0_ODL1_CONFIG 0x901082B -#define OB3_ODL0_CONFIG 0xC01082A -#define OB3_ODL1_CONFIG 0xC01082B +#define OB_ODL_OFFSET(brick_index) \ + ((((brick_index - 2) >> 1) * 0x3000000) + ((brick_index == 3 || brick_index == 4) ? 1 : 0)) + +#define OB_ODL_CONFIG(brick_index) \ + (0x901082A + OB_ODL_OFFSET(brick_index)) #define OB_ODL_CONFIG_RESET PPC_BIT(0) #define OB_ODL_CONFIG_VERSION PPC_BITMASK(2, 7) #define OB_ODL_CONFIG_TRAIN_MODE PPC_BITMASK(8, 11) @@ -737,26 +738,17 @@ void npu2_scom_write(uint64_t gcid, uint64_t scom_base, #define OB_ODL_CONFIG_PHY_CNTR_LIMIT PPC_BITMASK(20, 23) #define OB_ODL_CONFIG_DEBUG_ENABLE PPC_BIT(33) #define OB_ODL_CONFIG_FWD_PROGRESS_TIMER PPC_BITMASK(40, 43) - -#define OB0_ODL0_STATUS 0x901082C -#define OB0_ODL1_STATUS 0x901082D -#define OB3_ODL0_STATUS 0xC01082C -#define OB3_ODL1_STATUS 0xC01082D +#define OB_ODL_STATUS(brick_index) \ + (0x901082C + OB_ODL_OFFSET(brick_index)) #define OB_ODL_STATUS_TRAINED_MODE PPC_BITMASK(0,3) #define OB_ODL_STATUS_RX_TRAINED_LANES PPC_BITMASK(16, 23) #define OB_ODL_STATUS_TX_TRAINED_LANES PPC_BITMASK(24, 31) #define OB_ODL_STATUS_TRAINING_STATE_MACHINE PPC_BITMASK(49, 51) - -#define OB0_ODL0_TRAINING_STATUS 0x901082E -#define OB0_ODL1_TRAINING_STATUS 0x901082F -#define OB3_ODL0_TRAINING_STATUS 0xC01082E -#define OB3_ODL1_TRAINING_STATUS 0xC01082F +#define OB_ODL_TRAINING_STATUS(brick_index) \ + (0x901082E + OB_ODL_OFFSET(brick_index)) #define OB_ODL_TRAINING_STATUS_STS_RX_PATTERN_B PPC_BITMASK(8, 15) - -#define OB0_ODL0_ENDPOINT_INFO 0x9010832 -#define OB0_ODL1_ENDPOINT_INFO 0x9010833 -#define OB3_ODL0_ENDPOINT_INFO 0xC010832 -#define OB3_ODL1_ENDPOINT_INFO 0xC010833 +#define OB_ODL_ENDPOINT_INFO(brick_index) \ + (0x9010832 + OB_ODL_OFFSET(brick_index)) /* Registers and bits used to clear the L2 and L3 cache */ #define L2_PRD_PURGE_CMD_REG 0x1080E |