core/pci: Only hack class code for root ports

Currently we apply a hack to devices directly under a PHB which sets
the class code shown in the DT to that of a generic PCI-PCI bridge.
This is done to work around a bug in some IBM PHBs where the root port
had an incorrect class code. This has the side effect of forcing the
class code of any devices on a root bus to that of a PCI-PCI bridge
including NVLink and OpenCAPI devices which causes them to be mis-labed
in the Skiboot PCI Summary.

Fix this by only appling the hack to PCIe devices that are marked as
root ports and add a description string for the 0680 class code that
we use for nvlink device.

Signed-off-by: Oliver O'Halloran <oohall@gmail.com>

1 files changed, 1 insertions, 1 deletions

diff --git a/core/pci.c b/core/pci.c
index cd6b9f3..9ee70f4 100644
--- a/core/pci.c
+++ b/core/pci.c
@@ -1570,7 +1570,7 @@ static void __noinline pci_add_one_device_node(struct phb *phb,
 	 * uses prefers to read the class code from the DT rather than
 	 * re-reading config space we can hack around it here.
 	 */
-	if (is_pcie && parent_node == phb->dt_node)
+	if (is_pcie && pd->dev_type == PCIE_TYPE_ROOT_PORT)
 		rev_class = (rev_class & 0xff) | 0x6040000;
 	cname = pci_class_name(rev_class >> 8);