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| author | Reza Arbab <arbab@linux.ibm.com> | 2019-08-20 16:12:55 -0500 |
|---|---|---|
| committer | Oliver O'Halloran <oohall@gmail.com> | 2019-08-23 16:50:47 +1000 |
| commit | 38e1c73fbac2cdd36f03eccb5a4ed069fcd09efd (patch) | |
| tree | c02d269c1f89dab3ba74f1fd4b7db8f0d571aa6b | |
| parent | f945230bf8605d3e2565352c283a67fb43555d41 (diff) | |
| download | skiboot-38e1c73fbac2cdd36f03eccb5a4ed069fcd09efd.zip skiboot-38e1c73fbac2cdd36f03eccb5a4ed069fcd09efd.tar.gz skiboot-38e1c73fbac2cdd36f03eccb5a4ed069fcd09efd.tar.bz2 | |
npu3: Delay enablement of DL parity checking
Currently, we turn on TX and PRI parity checking of the DL during NPU
initialization, while RX parity checking is not enabled until after link
training.
This behavior was prescribed for npu2, but on npu3 systems the logic has
changed such that we're getting early parity error checkstops.
To fix, only set the TX and PRI enable bits after training, consistent
with RX.
Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
| -rw-r--r-- | hw/npu3-hw-procedures.c | 12 | ||||
| -rw-r--r-- | hw/npu3-nvlink.c | 2 |
2 files changed, 8 insertions, 6 deletions
diff --git a/hw/npu3-hw-procedures.c b/hw/npu3-hw-procedures.c index 54f4b35..86067a0 100644 --- a/hw/npu3-hw-procedures.c +++ b/hw/npu3-hw-procedures.c @@ -557,9 +557,11 @@ static uint32_t reset_ntl(struct npu3_dev *dev) val = SETFIELD(NPU3_NTL_PRI_CFG_NDL, 0ull, dev->index); npu3_write(npu, NPU3_NTL_PRI_CFG(dev->index), val); - /* Disable RX parity checking */ + /* Disable parity checking */ val = npu3_read(npu, NPU3_NTL_MISC_CFG2(dev->index)); - val &= ~NPU3_NTL_MISC_CFG2_NDL_RX_PARITY_ENA; + val &= ~(NPU3_NTL_MISC_CFG2_NDL_RX_PARITY_ENA | + NPU3_NTL_MISC_CFG2_NDL_TX_PARITY_ENA | + NPU3_NTL_MISC_CFG2_NDL_PRI_PARITY_ENA); npu3_write(npu, NPU3_NTL_MISC_CFG2(dev->index), val); if (dev->type == NPU3_DEV_TYPE_NVLINK) @@ -636,9 +638,11 @@ static uint32_t reset_ntl_finish(struct npu3_dev *dev) { if (npu3_dev_fence_get(dev) != NPU3_NTL_CQ_FENCE_STATUS_NONE) return NPU3_PROC_INPROGRESS; - /* Enable RX parity checking */ + /* Enable parity checking */ val = npu3_read(npu, NPU3_NTL_MISC_CFG2(dev->index)); - val |= NPU3_NTL_MISC_CFG2_NDL_RX_PARITY_ENA; + val |= NPU3_NTL_MISC_CFG2_NDL_RX_PARITY_ENA | + NPU3_NTL_MISC_CFG2_NDL_TX_PARITY_ENA | + NPU3_NTL_MISC_CFG2_NDL_PRI_PARITY_ENA; npu3_write(npu, NPU3_NTL_MISC_CFG2(dev->index), val); if (dev->type == NPU3_DEV_TYPE_NVLINK) diff --git a/hw/npu3-nvlink.c b/hw/npu3-nvlink.c index 35f68a8..6969b89 100644 --- a/hw/npu3-nvlink.c +++ b/hw/npu3-nvlink.c @@ -928,8 +928,6 @@ static void npu3_dev_init_hw(struct npu3_dev *dev) reg = NPU3_NTL_MISC_CFG2(dev->index); val = npu3_read(npu, reg); val |= NPU3_NTL_MISC_CFG2_BRICK_ENABLE | - NPU3_NTL_MISC_CFG2_NDL_TX_PARITY_ENA | - NPU3_NTL_MISC_CFG2_NDL_PRI_PARITY_ENA | NPU3_NTL_MISC_CFG2_RCV_CREDIT_OVERFLOW_ENA; npu3_write(npu, reg, val); } |