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| author | Oliver O'Halloran <oohall@gmail.com> | 2019-08-23 18:12:09 +1000 |
|---|---|---|
| committer | Oliver O'Halloran <oohall@gmail.com> | 2019-08-23 18:15:38 +1000 |
| commit | 7b12d5489fcfd73ef7ec0cb27eff7f8a5f13b238 (patch) | |
| tree | 47677b6db56e702fc5f60b4168cc0bdd69a1eea5 | |
| parent | 8bb0ae357938d947d7f3bef6b12f4879db10ebe0 (diff) | |
| download | skiboot-7b12d5489fcfd73ef7ec0cb27eff7f8a5f13b238.zip skiboot-7b12d5489fcfd73ef7ec0cb27eff7f8a5f13b238.tar.gz skiboot-7b12d5489fcfd73ef7ec0cb27eff7f8a5f13b238.tar.bz2 | |
hw/lpc: Configure SerIRQ interrupts on P9P
We need to do the LPC SerIRQ mux configuration on P9P too. Without this
we don't get UART interrupts from the BMC which makes the UART console
*much* less responsive than it should be.
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
| -rw-r--r-- | hw/lpc.c | 7 |
1 files changed, 5 insertions, 2 deletions
@@ -905,7 +905,8 @@ void lpc_finalize_interrupts(void) for_each_chip(chip) { if (chip->lpc && chip->psi && (chip->type == PROC_CHIP_P9_NIMBUS || - chip->type == PROC_CHIP_P9_CUMULUS)) + chip->type == PROC_CHIP_P9_CUMULUS || + chip->type == PROC_CHIP_P9P)) lpc_create_int_map(chip->lpc, chip->psi->node); } } @@ -948,6 +949,7 @@ static void lpc_init_interrupts_one(struct proc_chip *chip) break; case PROC_CHIP_P9_NIMBUS: case PROC_CHIP_P9_CUMULUS: + case PROC_CHIP_P9P: /* On P9, we additionally setup the routing. */ lpc->has_serirq = true; for (i = 0; i < LPC_NUM_SERIRQ; i++) { @@ -1365,7 +1367,8 @@ void lpc_register_client(uint32_t chip_id, has_routes = chip->type == PROC_CHIP_P9_NIMBUS || - chip->type == PROC_CHIP_P9_CUMULUS; + chip->type == PROC_CHIP_P9_CUMULUS || + chip->type == PROC_CHIP_P9P; if (policy != IRQ_ATTR_TARGET_OPAL && !has_routes) { prerror("Chip doesn't support OS interrupt policy\n"); |