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2023-12-03MdePkg/Test: Add google tests for BaseLibPedro Falcato4-0/+118
Add GoogleTestBaseLib, which contains gtest unit tests for BaseLib. For now, only add checksum tests for CRC32C and CRC16; these tests check for correctness on various inputs using precomputed hashes. Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Pedro Falcato <pedro.falcato@gmail.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
2023-12-03MdePkg/BaseLib: Fix CRC16-ANSI calculationPedro Falcato2-2/+7
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4609 The current CalculateCrc16Ansi implementation does the following: 1) Invert the passed checksum 2) Calculate the new checksum by going through data and using the lookup table 3) Invert it back again This emulated my design for CalculateCrc32c, where 0 is passed as the initial checksum, and it inverts in the end. However, CRC16 does not invert the checksum on input and output. So this is incorrect. Fix the problem by not inverting input checksums nor output checksums. Callers should now pass CRC16ANSI_INIT as the initial value instead of "0". This is a breaking change. This problem was found out-of-list when older ext4 filesystems (that use crc16 checksums) failed to mount with "corruption". Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Pedro Falcato <pedro.falcato@gmail.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
2023-11-09MdePkg/Tdx.h: Add TDVMCALL_STATUS_RETRYCeping Sun1-0/+2
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4572 TDVMCALL_STATUS_RETRY is defined in GHCI spec section 2.4.1. Reference: [GHCI]: TDX Guest-Host-Communication Interface v1.0 https://cdrdv2.intel.com/v1/dl/getContent/726790 Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Erdem Aktas <erdemaktas@google.com> Cc: James Bottomley <jejb@linux.ibm.com> Cc: Min Xu <min.m.xu@intel.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Cc: Michael Roth <michael.roth@amd.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Signed-off-by: Ceping Sun <cepingx.sun@intel.com>
2023-11-09MdePkg/BaseLib: Update TdVmcall to always output the value in R11Ceping Sun1-3/+1
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4572 According to section 3.2 of the [GHCI] spec, if the return status of MapGPA is "TDG.VP.VMCALL_RETRY", TD must retry this operation for the pages in the region starting at the GPA specified in R11. Currently, TDVF has not handled the retry results and always clears the R11 on unsuccessful return status. For this, the TdVmcall needs to output the value of R11 on unsuccessful return status to handle the retry results of MapGPA. Reference: [GHCI]: TDX Guest-Host-Communication Interface v1.0 https://cdrdv2.intel.com/v1/dl/getContent/726790 Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Erdem Aktas <erdemaktas@google.com> Cc: James Bottomley <jejb@linux.ibm.com> Cc: Min Xu <min.m.xu@intel.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Cc: Michael Roth <michael.roth@amd.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Signed-off-by: Ceping Sun <cepingx.sun@intel.com>
2023-11-06MdePkg: IndustryStandard: Add DLL CharacteristicsJoey Vagedes1-1/+16
Add the bit masks for DLL Characteristics, used within the optional header of a PE, to the PeImage.h header file. Update the Visual Studio, Microsoft Portable Executable and Common Object File Format Specification, and the PE/COFF Specification to the latest version. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Joey Vagedes <joeyvagedes@gmail.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Rebecca Cran <rebecca@bsdio.com>
2023-10-31MdePkg ACPI65: Add 0x0B/PRM to Generic Address StructureJinlong Xu1-0/+1
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4567 ACPI_Spec_6_5_Aug29 Table 5.1, add 0x0B/Platform Runtime Mechanism (PRM) in Address Space ID of Generic Address Structure (GAS) Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Signed-off-by: Jinlong Xu <jinlong.xu@intel.com> Message-Id: <20231020111348.2921-1-jinlong.xu@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
2023-10-30MdePkg: MADT: Add TRBE interrupt to GICCSami Mujawar1-0/+1
The ASWG ECR 2303 introduces a new field 'TRBE interrupt' to GICC structure in ACPI 6.5. The Trace Buffer Extension (TRBE) interrupt is a Processor Private interrupt (PPI) and is used to specify a platform-specific interrupt to signal TRBE events. Signed-off-by: Sami Mujawar <sami.mujawar@arm.com> Reviewed-by: Pierre Gondois <pierre.gondois@arm.com> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com>
2023-10-30MdePkg: MADT: Add Online capable flag in GICCSami Mujawar1-1/+2
Bugzilla: 3706 'Code First - MADT GICC new flags' On ARM systems physical CPU hotplug is not supported. All CPUs are considered present and this is true throughout the system uptime. The ECR 2285 introduces a new 'online-capable' flag in the GICC structure flags in ACPI 6.5, to signal firmware policy (CPU is not enabled but it can be enabled and onlined). This enables OSPM to support virtual CPU hotplug (on virtual platforms for instance). This ECR also updates the MADT table revision to 6 to reflect the ACPI 6.5 changes. Therefore, update the MADT table revision to match the value as specified in ACPI 6.5. Signed-off-by: Sami Mujawar <sami.mujawar@arm.com> Reviewed-by: Pierre Gondois <pierre.gondois@arm.com> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com>
2023-10-27MdePkg: Apply uncrustify formatting to relevant filesVivian Nowka-Keane11-458/+463
Apply uncrustify formatting to GoogleTest cpp and header files. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Vivian Nowka-Keane <vnowkakeane@linux.microsoft.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
2023-10-26MdePkg/Include: Definitions of IPMI Get System Interface CapabilitiesAbner Chang1-0/+8
Define the structure for IPMI Get System Interface Capabilities command (0x57) Signed-off-by: Abner Chang <abner.chang@amd.com> Cc: Abdul Lateef Attar <AbdulLateef.Attar@amd.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Nickle Wang <nicklew@nvidia.com>
2023-10-26MdePkg: Add Cxl20.h into IndustryStandardChris Li2-1/+464
1) Add CXL 2.0 header file to comply with CXL 2.0 specification 2) CXL 2.0 header will embed Cxl11.h 3) Updated Cxl.h to point to 2.0 header file Signed-off-by: Chris Li <chrisli@os.amperecomputing.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Cc: Ray Ni <ray.ni@intel.com> Cc: Yao, Jiewen <jiewen.yao@intel.com> Cc: Nong, Foster <foster.nong@intel.com> Cc: Kinney, Michael D <michael.d.kinney@intel.com>
2023-10-25MdePkg/Pldm.h: Add define for the PLDM response flagKonstantin Aladyshev1-0/+1
The PLDM protocol uses Request bit to help differentiate between PLDM request and response messages. Currently the Pldm.h header only have a flag for the request message. Add a flag for the response message as well. Signed-off-by: Konstantin Aladyshev <aladyshev22@gmail.com>
2023-10-25MdePkg/Mctp.h: Correct typo in structure member nameKonstantin Aladyshev1-1/+1
Correct MCTP_TRANSPORT_HEADER structure field 'SourceEndpointIdId' to 'SourceEndpointId'. Signed-off-by: Abner Chang <abner.chang@amd.com> Signed-off-by: Konstantin Aladyshev <aladyshev22@gmail.com>
2023-10-23MdePkg: CI: Add PrEval entryJoey Vagedes1-0/+3
Adds a PrEval entry to the package's ci.yaml file which is used to verify if the package uses a particular library instance when that library instance file (INF) is updated. When a library instance file (INF) is updated, PrEval will review each package's DSC as described in the ci.yaml file to determine if the package uses said library instance. If the package does use the library instance, it will be built and tested to ensure the package is not broken from the change. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Joey Vagedes <joeyvagedes@gmail.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
2023-10-19MdePkg/Test: Add DevicePathLib host test moduleMateusz Albecki6-1/+1073
This commit adds host-based unit tests for device path lib. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@bysoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Mateusz Albecki <mateusz.albecki@intel.com> Reviewed-by: Michael D Kinney <Michael.d.kinney@intel.com>
2023-10-19MdePkg/UefiDevicePathLib: Fix AcpiEx print logicMateusz Albecki1-27/+45
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4555 Add logic that checks if the code doesn't overflow ACPI_EXTENDED_HID_DEVICE_PATH node when searching for optional strings. If the string is not provided in the device path node default value of "\0" is used. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@bysoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Mateusz Albecki <mateusz.albecki@intel.com> Reviewed-by: Michael D Kinney <Michael.d.kinney@intel.com>
2023-10-04MdePkg/DxeRngLib: Add missing GUID declaration in infPierre Gondois1-0/+1
Add missing GUID declaration in DxeRngLib.inf. Fixes: bd1f0eecc1df ("MdePkg/DxeRngLib: Request raw algorithm instead of default") Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com> Tested-by: Leif Lindholm <quic_llindhol@quicinc.com> Acked-by: Ard Biesheuvel <ardb@kernel.org>
2023-10-03MdePkg/BaseLib: fix typo in Arm SetJumpLeif Lindholm1-1/+1
RO -> R0 Signed-off-by: Leif Lindholm <quic_llindhol@quicinc.com> Reported-by: Philippe Mathieu-Daudé <philmd@linaro.org> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Sami Mujawar <sami.mujawar@arm.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
2023-10-02MdePkg/BaseLib: ensure ARM LongJump never returns 0Leif Lindholm2-0/+4
The ARM implementation of InternalLongJump always returned the value Value - but it is not supposed to ever return 0. Add the test to prevent that, and return 1 if Value is 0 - as is already present in AArch64. Signed-off-by: Leif Lindholm <quic_llindhol@quicinc.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Sami Mujawar <sami.mujawar@arm.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
2023-10-02MdePkg/BaseLib: correct register sizes in AArch64 SetJump/LongJumpLeif Lindholm2-8/+8
Both in SetJump and in InternalLongJump, 32-bit w register views were used for the UINTN return value. In SetJump, this did not cause errors; it was only counterintuitive. But in InternalLongJump, it meant the top 32 bits of Value were stripped off. Change all of these to use the 64-bit x register views. Signed-off-by: Leif Lindholm <quic_llindhol@quicinc.com> Reanimated-by: Andrei Warkentin <andrei.warkentin@intel.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Sami Mujawar <sami.mujawar@arm.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com> Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com>
2023-10-02MdePkg/BaseLib: use normal register init in ARM SetJump implementationsLeif Lindholm2-2/+2
There may be architectures on which there are benefits to eor r0, r0(, r0) but ARM was never one of them. Change to more readable mov r0, #0 instead. Signed-off-by: Leif Lindholm <quic_llindhol@quicinc.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Sami Mujawar <sami.mujawar@arm.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
2023-10-02MdePkg/BaseLib: add ASSERT in ARM* SetJump implementationsLeif Lindholm2-0/+16
The SetJump comment header states that: If JumpBuffer is NULL, then ASSERT(). However, this was not currently done. Add a call to InternalAssertJumpBuffer. Signed-off-by: Leif Lindholm <quic_llindhol@quicinc.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Sami Mujawar <sami.mujawar@arm.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
2023-10-02MdePkg/BaseLib: fix comments in ARM* SetJump/LongJump implementationsLeif Lindholm4-8/+4
Drop redundant comment about IPF (clearly copied across from now deleted code). Also change "Instead is resumes execution" -> "Instead it resumes execution" Signed-off-by: Leif Lindholm <quic_llindhol@quicinc.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Sami Mujawar <sami.mujawar@arm.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
2023-09-26UefiPayloadPkg: Add FIT supportBrucex.Wang2-7/+7
Provide Fit format for UniversalPayload, developer can use argument "--Fit" to build UniversalPayload.fit Cc: Guo Dong <guo.dong@intel.com> Cc: Sean Rhodes <sean@starlabs.systems> Cc: James Lu <james.lu@intel.com> Cc: Gua Guo <gua.guo@intel.com> Reviewed-by: Gua Guo <gua.guo@intel.com> Signed-off-by: BruceX Wang <brucex.wang@intel.com>
2023-09-26MdePkg/BaseFdtLib: Add Fdt function.Brucex.Wang2-0/+74
Add FdtGetName() and FdtNodeDepth() function. Cc: Benny Lin <benny.lin@intel.com> Cc: Gua Guo <gua.guo@intel.com> Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: James Lu <james.lu@intel.com> Reviewed-by: Benny Lin <benny.lin@intel.com> Reviewed-by: Gua Guo <gua.guo@intel.com> Signed-off-by: BruceX Wang <brucex.wang@intel.com>
2023-09-21RISCV: Fix InternalLongJump to return correct valueAndrei Warkentin1-5/+2
InternalLongJump was not returning the 2nd parameter passed to LongJmp (Value) as the return value from SetJmp. Seen with code compiled with -Os, where an LongJmp (Buffer, -1) somehow translated to SetJmp returning 0... Cc: Yong Li <yong.li@intel.com> Cc: Sunil V L <sunilvl@ventanamicro.com> Cc: Tuan Phan <tphan@ventanamicro.com> Cc: Daniel Schaefer <git@danielschaefer.me> Signed-off-by: Andrei Warkentin <andrei.warkentin@intel.com> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
2023-09-19RedfishPkg/RedfishRestExDxe: return HTTP status code to caller.Nickle Wang1-1/+2
Return unsupported HTTP status code to caller so caller can handle HTTP error status code. Current implementation only return EFI error to caller. Without knowing the HTTP status code, caller has trouble to handle HTTP request failure. Signed-off-by: Nickle Wang <nicklew@nvidia.com> Cc: Abner Chang <abner.chang@amd.com> Cc: Igor Kulchytskyy <igork@ami.com> Cc: Nick Ramirez <nramirez@nvidia.com> Cc: Mike Maslenkin <mike.maslenkin@gmail.com> Reviewed-by: Igor Kulchytskyy <igork@ami.com> Reviewed-by: Abner Chang <abner.chang@amd.com> Acked-by: Mike Maslenkin <mike.maslenkin@gmail.com>
2023-09-08MdePkg/SmBios.h: Add New Intel Processor familyAvinash Bhargava1-0/+1
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4547 Add New Intel Processor family for SMBIOS Type 4 Hex value - 16h Name - Intel(R) Processor Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Dandan Bi <dandan.bi@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Zhichao Gao <zhichao.gao@intel.com> Cc: Benny Lin <benny.lin@intel.com> Cc: Gua Guo <gua.guo@intel.com> Cc: Prakashan Krishnadas Veliyathuparambil <krishnadas.veliyathuparambil.prakashan@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Signed-off-by: Avinash Bhargava <avinash.bhargava@intel.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
2023-09-08MdePkg/Library/TdxLib: Remove unnecessary comparisonMichael Kubacki1-1/+1
Removes the comparison since unsigned values are always greater than or equal to 0. See the following CodeQL query for more info: /cpp/cpp-unsigned-comparison-zero/ Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Rebecca Cran <rebecca@bsdio.com> Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>
2023-09-08MdePkg/Rng: Add GetRngGuid() to RngLibPierre Gondois7-0/+168
The EFI_RNG_PROTOCOL can use the RngLib. The RngLib has multiple implementations, some of them are unsafe (e.g. BaseRngLibTimerLib). To allow the RngDxe to detect when such implementation is used, add a GetRngGuid() function to the RngLib. Signed-off-by: Pierre Gondois <pierre.gondois@arm.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com> Acked-by: Ard Biesheuvel <ardb@kernel.org> Tested-by: Kun Qin <kun.qin@microsoft.com>
2023-09-08MdePkg/Rng: Add GUID to describe Arm Rndr Rng algorithmsPierre Gondois2-0/+11
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4441 The EFI_RNG_PROTOCOL can rely on the RngLib. The RngLib has multiple implementations, some of them are unsafe (e.g. BaseRngLibTimerLib). To allow the RngDxe to detect when such implementation is used, a GetRngGuid() function is added in a following patch. Prepare GetRngGuid() return values and add a gEfiRngAlgorithmArmRndr to describe a Rng algorithm accessed through Arm's RNDR instruction. [1] states that the implementation of this algorithm should be compliant to NIST SP900-80. The compliance is not guaranteed. [1] Arm Architecture Reference Manual Armv8, for A-profile architecture sK12.1 'Properties of the generated random number' Signed-off-by: Pierre Gondois <pierre.gondois@arm.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Acked-by: Ard Biesheuvel <ardb@kernel.org> Tested-by: Kun Qin <kun.qin@microsoft.com>
2023-09-08MdePkg/DxeRngLib: Request raw algorithm instead of defaultPierre Gondois1-1/+7
The DxeRngLib tries to generate a random number using the 3 NIST SP 800-90 compliant DRBG algorithms, i.e. 256-bits CTR, HASH and HMAC. If none of the call is successful, the fallback option is the default RNG algorithm of the EFI_RNG_PROTOCOL. This default algorithm might be an unsafe implementation. Try requesting the Raw algorithm before requesting the default one. Signed-off-by: Pierre Gondois <pierre.gondois@arm.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Acked-by: Ard Biesheuvel <ardb@kernel.org> Tested-by: Kun Qin <kun.qin@microsoft.com>
2023-09-08SecurityPkg/SecurityPkg.dec: Move PcdCpuRngSupportedAlgorithm to MdePkgPierre Gondois1-0/+5
In order to use PcdCpuRngSupportedAlgorithm in the MdePkg in a following patch and to avoid making the MdePkg dependent on another package, move PcdCpuRngSupportedAlgorithm to the MdePkg. As the Pcd is only used for AARCH64, place it in an AARCH64 specific sections. Signed-off-by: Pierre Gondois <pierre.gondois@arm.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com> Acked-by: Ard Biesheuvel <ardb@kernel.org> Acked-by: Jiewen Yao <Jiewen.yao@intel.com> Tested-by: Kun Qin <kun.qin@microsoft.com>
2023-09-08MdePkg: Add deprecated warning to BaseRngLibTimerPierre Gondois2-0/+23
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4504 To keep the MdePkg self-contained and avoid dependencies on GUIDs defined in other packages, the BaseRngLibTimer was moved to the MdePkg. Add a constructor to warn and request to use the MdeModulePkg implementation. Signed-off-by: Pierre Gondois <pierre.gondois@arm.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com> Acked-by: Ard Biesheuvel <ardb@kernel.org> Tested-by: Kun Qin <kun.qin@microsoft.com>
2023-09-08MdePkg/Library/BaseRngLib: Fix include guardMichael Kubacki1-0/+1
The include guard is incomplete and does not define the macro. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Rebecca Cran <rebecca@bsdio.com> Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com> Reviewed-by: Rebecca Cran <rebecca@os.amperecomputing.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
2023-08-31MdePkg: Add ProcessorUpgradeSocket definitions from SMBIOS 3.7.0Eduardo Cuevas Farfan1-3/+11
This patch adds below definitions from SMBIOS 3.7.0 into Smbios.h - ProcessorUpgradeSocketAM5 - ProcessorUpgradeSocketSP5 - ProcessorUpgradeSocketSP6 - ProcessorUpgradeSocketBGA883 - ProcessorUpgradeSocketBGA1190 - ProcessorUpgradeSocketBGA4129 - ProcessorUpgradeSocketLGA4710 - ProcessorUpgradeSocketLGA7529 Signed-off-by: Eduardo Cuevas Farfan <eduardo.cuevas.farfan@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
2023-08-09MedPkg/Include: Add PCI_EXPRESS_EXTENDED_CAPABILITY_DVSEC_IDFoster Nong1-0/+2
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=4515 Add PCI_EXPRESS_EXTENDED_CAPABILITY_DESIGNATED_VENDOR_SPECIFIC_ID 0x0023 in PciExpress40.h Signed-off-by: Foster Nong <foster.nong@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Ray Ni <ray.ni@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
2023-08-07MdePkg: Add new status codes to PrintLibNate DeSimone1-3/+7
PrintLib does not correctly decode the follow status codes: 1. EFI_IP_ADDRESS_CONFLICT 2. EFI_HTTP_ERROR 3. EFI_WARN_FILE_SYSTEM 4. EFI_WARN_RESET_REQUIRED These missing status codes have been added. Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
2023-08-07MdePkg: Add missing status codesNate DeSimone2-0/+12
REF: https://uefi.org/specs/UEFI/2.10/Apx_D_Status_Codes.html Upon review it has been found that MdePkg is missing two status code definitions: 1. EFI_IP_ADDRESS_CONFLICT - Added in UEFI Spec v2.5 2. EFI_WARN_RESET_REQUIRED - Added in UEFI Spec v2.6 These missing status codes have been added. Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
2023-07-24MdePkg/Include/IndustryStandard: Remove VS20xx workaroundMichael D Kinney1-5/+0
Remove workaround for the redefinition of the type RUNTIME_FUNCTION that is generated when building with VS20xx tool chains and using windows include files. The correct location for this fix is in the EmulatorPkg in the WinInclude.h file that addresses all the name collisions between edk2 types and windows types. The commit that added the workaround is: https://github.com/tianocore/edk2/commit/ff52068d9261b9391d75b83a2a4e40e040f3b6eb Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Rebecca Cran <rebecca@bsdio.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Rebecca Cran <rebecca@bsdio.com>
2023-07-15MdePkg/Register: RISC-V: Add satp mode bits shift definitionTuan Phan1-3/+4
The satp mode bits shift is used cross modules. It should be defined in one place. Signed-off-by: Tuan Phan <tphan@ventanamicro.com> Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
2023-07-15MdePkg/BaseLib: RISC-V: Support getting satp register valueTuan Phan2-0/+13
Add an API to retrieve satp register value. Signed-off-by: Tuan Phan <tphan@ventanamicro.com> Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
2023-07-03MdePkg: Adds AMD SMRAM save state mapAbdul Lateef Attar2-1/+197
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4182 Adds an SMM SMRAM save-state map for AMD processors. SMRAM save state maps for the AMD processor family are now supported. Save state map structure is added based on AMD64 Architecture Programmer's Manual, Volume 2, Section 10.2. The AMD legacy save state map for 32-bit architecture is defined. The AMD64 save state map for 64-bit architecture is defined.  Also added Amd/SmramSaveStateMap.h to IgnoreFiles of EccCheck, because structures defined in this file are derived from Intel/SmramSaveStateMap.h. Cc: Paul Grimes <paul.grimes@amd.com> Cc: Abner Chang <abner.chang@amd.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Abdul Lateef Attar <abdattar@amd.com> Reviewed-by: Abner Chang <abner.chang@amd.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
2023-06-23MdePkg: PiStatusCode: Add TPM subclass definition to MdePkgKun Qin1-0/+1
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3966 This change introduces a new peripheral subclass definition from PI specification v1.8. The new subclass definition will cover system reboot events under the status reports from Trusted Platform Modules (TPMs). These definition could provide helpful datapoints to OEMs to analyze system security state and healthiness, as well as avoid definition collision with other existing peripheral subclass definitions. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Kun Qin <kuqin12@gmail.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
2023-06-23MdePkg: PiStatusCode: Add new Host Software class Error Code to MdePkgKun Qin1-20/+21
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3794 This change introduces a new error code definitions under Host Software class according to PI specification v1.8. The new error code definition will cover system reboot events under the conditions of inconsistent memory map from one boot to another. These error codes could provide helpful datapoints to OEMs to investigate and prevent system failures in general. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Kun Qin <kuqin12@gmail.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
2023-06-21MdePkg: Code optimization to SMM InternalAllocateAlignedPagesduntan1-1/+1
This commit is code optimization to InternalAllocateAlignedPages of SmmMemoryAllocationLib which can reduce free memory fragments. Also it can reduce one pre-allocation page. Let's take a simple example: The expected pages size is 8KB, Alignment value is 8KB. In original InternalAllocateAlignedPages(), the first step is to allocate 4 pages and then find the first 8KB-aligned address in allocated 4 pages. If the upper limit address of allocated 4 pages is already 8KB aligned, then the allocated 4 pages contains two 8KB-aligned 8KB ranges. The lower 2 pages will be selected and removed from free pages. Then the higher 2 pages will be free. Since the whole memory allocation is from high address to low address, then the higher 2 pages cann't be merged with other free pages, causing the free memory fragments. However, when only allocate 3(2+2-1) pages, we can avoid the free memory fragments in specific case. Also 3 pages must contain a 8KB-aligned 8KB range, which meets the requirement. If the upper limit address of allocated 3 pages is 8KB-aligned, then the higher 2 pages range of allocated 3 pages is 8KB-aligned and will be selected and removed from free pages. The remaining lower one page of allocated 3 pages will be free and merged with left lower free memory. This can reduce free memory fragments in smm. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Ray Ni <ray.ni@intel.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com>
2023-06-15UefiCpuPkg: RISC-V: TimerLib: Fix delay function to use 64-bitTuan Phan1-1/+0
The timer compare register is 64-bit so simplifying the delay function. Cc: Andrei Warkentin <andrei.warkentin@intel.com> Signed-off-by: Tuan Phan <tphan@ventanamicro.com> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
2023-06-06MdePkg/BaseLib: Add SpeculationBarrier implementation for RiscV64Yong Li2-0/+35
Implement the SpeculationBarrier with implementations consisting of fence instruction which provides finer-grain memory orderings. Perform Data Barrier in RiscV: fence rw,rw Perform Instruction Barrier in RiscV: fence.i; fence r,r More detail is in Appendix A: RVWMO Explanatory Material in https://github.com/riscv/riscv-isa-manual This API is first introduced in the below commits for IA32 and x64 https://github.com/tianocore/edk2/commit/d9f1cac51bd354507e880e614d11a1dc160d38a3 https://github.com/tianocore/edk2/commit/e83d841fdc2878959185c4c6cc38a7a1e88377a4 and below the commit for ARM and AArch64 implementation https://github.com/tianocore/edk2/commit/c0959b4426b2da45cdb8146a5116bb4fd9b86534 This commit is to add the RiscV64 implementation which will be used by variable service under Variable/RuntimeDxe Cc: Andrei Warkentin <andrei.warkentin@intel.com> Cc: Evan Chai <evan.chai@intel.com> Cc: Sunil V L <sunilvl@ventanamicro.com> Cc: Tuan Phan <tphan@ventanamicro.com> Signed-off-by: Yong Li <yong.li@intel.com> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
2023-06-06MdePkg ACPI65: Update MADT Revision pre ACPI Spec 6.5Aryeh Chen1-1/+1
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4474 ACPI_Spec_6_5_Aug29 Table 5.19 page 128 that MADT Revision field is 6. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Signed-off-by: Aryeh Chen <aryeh.chen@intel.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Tested-by: Aryeh Chen <aryeh.chen@intel.com>
2023-06-01MdePkg/PeImage.h: add bits from BaseTools versionGerd Hoffmann1-0/+31
The BaseTools and MdePkg versions of PeImage.h diverged over time, add some missing bits to the MdePkg header file in preparation for removing the BaseTools version. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Rebecca Cran <rebecca@bsdio.com>
generated by cgit v1.1 at 2024-11-13 14:01:14 +0000