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| author | Tuan Phan <tphan@ventanamicro.com> | 2023-07-14 12:08:19 -0700 |
|---|---|---|
| committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2023-07-15 14:10:18 +0000 |
| commit | fbec9aec00c2cc10de439f2f0c3accb52488d32f (patch) | |
| tree | 8d4a4b2a4fd99133e0dec6aee51cfb5a3ec91923 /MdePkg | |
| parent | 7178047402c07d369a2a3a0b0e5118c5e3d90ddc (diff) | |
| download | edk2-fbec9aec00c2cc10de439f2f0c3accb52488d32f.zip edk2-fbec9aec00c2cc10de439f2f0c3accb52488d32f.tar.gz edk2-fbec9aec00c2cc10de439f2f0c3accb52488d32f.tar.bz2 | |
MdePkg/Register: RISC-V: Add satp mode bits shift definition
The satp mode bits shift is used cross modules. It should be defined
in one place.
Signed-off-by: Tuan Phan <tphan@ventanamicro.com>
Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com>
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
Diffstat (limited to 'MdePkg')
| -rw-r--r-- | MdePkg/Include/Register/RiscV64/RiscVEncoding.h | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/MdePkg/Include/Register/RiscV64/RiscVEncoding.h b/MdePkg/Include/Register/RiscV64/RiscVEncoding.h index 5c2989b..2bde8db 100644 --- a/MdePkg/Include/Register/RiscV64/RiscVEncoding.h +++ b/MdePkg/Include/Register/RiscV64/RiscVEncoding.h @@ -58,9 +58,10 @@ #define PRV_S 1UL
#define PRV_M 3UL
-#define SATP64_MODE 0xF000000000000000ULL
-#define SATP64_ASID 0x0FFFF00000000000ULL
-#define SATP64_PPN 0x00000FFFFFFFFFFFULL
+#define SATP64_MODE 0xF000000000000000ULL
+#define SATP64_MODE_SHIFT 60
+#define SATP64_ASID 0x0FFFF00000000000ULL
+#define SATP64_PPN 0x00000FFFFFFFFFFFULL
#define SATP_MODE_OFF 0UL
#define SATP_MODE_SV32 1UL
|