diff options
Diffstat (limited to 'MdePkg/Include')
35 files changed, 1502 insertions, 99 deletions
diff --git a/MdePkg/Include/AArch64/AsmMacroLib.h b/MdePkg/Include/AArch64/AsmMacroLib.h new file mode 100644 index 0000000..a5c8635 --- /dev/null +++ b/MdePkg/Include/AArch64/AsmMacroLib.h @@ -0,0 +1,56 @@ +/** @file
+ Macros to work around lack of Clang support for LDR register, =expr
+
+ Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+ Portions copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.<BR>
+ Copyright (c) 2016, Linaro Ltd. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef ASM_MACRO_IO_LIBV8_H_
+#define ASM_MACRO_IO_LIBV8_H_
+
+// CurrentEL : 0xC = EL3; 8 = EL2; 4 = EL1
+// This only selects between EL1 and EL2, else we die.
+// Provide the Macro with a safe temp xreg to use.
+#define EL1_OR_EL2(SAFE_XREG) \
+ mrs SAFE_XREG, CurrentEL ;\
+ cmp SAFE_XREG, #0x8 ;\
+ b.gt . ;\
+ b.eq 2f ;\
+ cbnz SAFE_XREG, 1f ;\
+ b . ;// We should never get here
+
+#define _ASM_FUNC(Name, Section) \
+ .global Name ; \
+ .section #Section, "ax" ; \
+ .type Name, %function ; \
+ Name: ; \
+ AARCH64_BTI(c)
+
+#define _ASM_FUNC_ALIGN(Name, Section, Align) \
+ .global Name ; \
+ .section #Section, "ax" ; \
+ .type Name, %function ; \
+ .balign Align ; \
+ Name: ; \
+ AARCH64_BTI(c)
+
+#define ASM_FUNC(Name) _ASM_FUNC(ASM_PFX(Name), .text. ## Name)
+
+#define ASM_FUNC_ALIGN(Name, Align) \
+ _ASM_FUNC_ALIGN(ASM_PFX(Name), .text. ## Name, Align)
+
+#define MOV32(Reg, Val) \
+ movz Reg, (Val) >> 16, lsl #16 ; \
+ movk Reg, (Val) & 0xffff
+
+#define MOV64(Reg, Val) \
+ movz Reg, (Val) >> 48, lsl #48 ; \
+ movk Reg, ((Val) >> 32) & 0xffff, lsl #32 ; \
+ movk Reg, ((Val) >> 16) & 0xffff, lsl #16 ; \
+ movk Reg, (Val) & 0xffff
+
+#endif // ASM_MACRO_IO_LIBV8_H_
diff --git a/MdePkg/Include/Arm/AsmMacroLib.h b/MdePkg/Include/Arm/AsmMacroLib.h new file mode 100644 index 0000000..2493a15 --- /dev/null +++ b/MdePkg/Include/Arm/AsmMacroLib.h @@ -0,0 +1,38 @@ +/** @file
+ Macros to work around lack of Apple support for LDR register, =expr
+
+ Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+ Copyright (c) 2011-2012, ARM Ltd. All rights reserved.<BR>
+ Copyright (c) 2016, Linaro Ltd. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef ASM_MACRO_IO_LIB_H_
+#define ASM_MACRO_IO_LIB_H_
+
+#define _ASM_FUNC(Name, Section) \
+ .global Name ; \
+ .section #Section, "ax" ; \
+ .type Name, %function ; \
+ .p2align 2 ; \
+ Name:
+
+#define ASM_FUNC(Name) _ASM_FUNC(ASM_PFX(Name), .text. ## Name)
+
+#define MOV32(Reg, Val) \
+ movw Reg, #(Val) & 0xffff ; \
+ movt Reg, #(Val) >> 16
+
+#define ADRL(Reg, Sym) \
+ movw Reg, #:lower16:(Sym) - (. + 16) ; \
+ movt Reg, #:upper16:(Sym) - (. + 12) ; \
+ add Reg, Reg, pc
+
+#define LDRL(Reg, Sym) \
+ movw Reg, #:lower16:(Sym) - (. + 16) ; \
+ movt Reg, #:upper16:(Sym) - (. + 12) ; \
+ ldr Reg, [pc, Reg]
+
+#endif // ASM_MACRO_IO_LIB_H_
diff --git a/MdePkg/Include/Base.h b/MdePkg/Include/Base.h index 7caebbe..363e0fe 100644 --- a/MdePkg/Include/Base.h +++ b/MdePkg/Include/Base.h @@ -1058,7 +1058,7 @@ typedef UINTN RETURN_STATUS; @retval FALSE The high bit of StatusCode is clear.
**/
-#define RETURN_ERROR(StatusCode) (((INTN)(RETURN_STATUS)(StatusCode)) < 0)
+#define RETURN_ERROR(StatusCode) (((RETURN_STATUS)(StatusCode)) >= MAX_BIT)
///
/// The operation completed successfully.
diff --git a/MdePkg/Include/Guid/ConformanceProfiles.h b/MdePkg/Include/Guid/ConformanceProfiles.h new file mode 100644 index 0000000..bf89ab6 --- /dev/null +++ b/MdePkg/Include/Guid/ConformanceProfiles.h @@ -0,0 +1,67 @@ +/** @file
+ GUIDs used for UEFI Conformance Profiles Table in the UEFI 2.10 specification.
+
+ Copyright (c) 2024, Arm Limited. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef CONFORMANCE_PROFILES_TABLE_GUID_H_
+#define CONFORMANCE_PROFILES_TABLE_GUID_H_
+
+//
+// This table allows the platform to advertise its UEFI specification conformance
+// in the form of pre-defined profiles. Each profile is identified by a GUID, with
+// known profiles listed in the section below.
+// The absence of this table shall indicate that the platform implementation is
+// conformant with the UEFI specification requirements, as defined in Section 2.6.
+// This is equivalent to publishing this configuration table with the
+// EFI_CONFORMANCE_PROFILES_UEFI_SPEC_GUID conformance profile.
+//
+#define EFI_CONFORMANCE_PROFILES_TABLE_GUID \
+ { \
+ 0x36122546, 0xf7e7, 0x4c8f, { 0xbd, 0x9b, 0xeb, 0x85, 0x25, 0xb5, 0x0c, 0x0b } \
+ }
+
+#pragma pack(1)
+
+typedef struct {
+ ///
+ /// Version of the table must be 0x1
+ ///
+ UINT16 Version;
+ ///
+ /// The number of profiles GUIDs present in ConformanceProfiles
+ ///
+ UINT16 NumberOfProfiles;
+ ///
+ /// An array of conformance profile GUIDs that are supported by this system.
+ /// EFI_GUID ConformanceProfiles[];
+ ///
+} EFI_CONFORMANCE_PROFILES_TABLE;
+
+#pragma pack()
+
+#define EFI_CONFORMANCE_PROFILES_TABLE_VERSION 0x1
+
+//
+// GUID defined in UEFI 2.10
+//
+#define EFI_CONFORMANCE_PROFILES_UEFI_SPEC_GUID \
+ { 0x523c91af, 0xa195, 0x4382, \
+ { 0x81, 0x8d, 0x29, 0x5f, 0xe4, 0x00, 0x64, 0x65 }}
+
+//
+// GUID defined in EBBR
+//
+#define EFI_CONFORMANCE_PROFILE_EBBR_2_1_GUID \
+ { 0xcce33c35, 0x74ac, 0x4087, \
+ { 0xbc, 0xe7, 0x8b, 0x29, 0xb0, 0x2e, 0xeb, 0x27 }}
+#define EFI_CONFORMANCE_PROFILE_EBBR_2_2_GUID \
+ { 0x9073eed4, 0xe50d, 0x11ee, \
+ { 0xb8, 0xb0, 0x8b, 0x68, 0xda, 0x62, 0xfc, 0x80 }}
+
+extern EFI_GUID gEfiConfProfilesTableGuid;
+extern EFI_GUID gEfiConfProfilesUefiSpecGuid;
+
+#endif
diff --git a/MdePkg/Include/IndustryStandard/Acpi51.h b/MdePkg/Include/IndustryStandard/Acpi51.h index 4241b8f..cdf9538 100644 --- a/MdePkg/Include/IndustryStandard/Acpi51.h +++ b/MdePkg/Include/IndustryStandard/Acpi51.h @@ -1760,6 +1760,7 @@ typedef struct { #define EFI_ACPI_5_1_EINJ_EXECUTE_OPERATION 0x05
#define EFI_ACPI_5_1_EINJ_CHECK_BUSY_STATUS 0x06
#define EFI_ACPI_5_1_EINJ_GET_COMMAND_STATUS 0x07
+#define EFI_ACPI_5_1_EINJ_SET_ERROR_TYPE_WITH_ADDRESS 0x08
#define EFI_ACPI_5_1_EINJ_TRIGGER_ERROR 0xFF
///
diff --git a/MdePkg/Include/IndustryStandard/Acpi60.h b/MdePkg/Include/IndustryStandard/Acpi60.h index 3757d3f..d545de1 100644 --- a/MdePkg/Include/IndustryStandard/Acpi60.h +++ b/MdePkg/Include/IndustryStandard/Acpi60.h @@ -1947,6 +1947,7 @@ typedef struct { #define EFI_ACPI_6_0_EINJ_EXECUTE_OPERATION 0x05
#define EFI_ACPI_6_0_EINJ_CHECK_BUSY_STATUS 0x06
#define EFI_ACPI_6_0_EINJ_GET_COMMAND_STATUS 0x07
+#define EFI_ACPI_6_0_EINJ_SET_ERROR_TYPE_WITH_ADDRESS 0x08
#define EFI_ACPI_6_0_EINJ_TRIGGER_ERROR 0xFF
///
diff --git a/MdePkg/Include/IndustryStandard/Acpi61.h b/MdePkg/Include/IndustryStandard/Acpi61.h index c3facc6..5100d8b 100644 --- a/MdePkg/Include/IndustryStandard/Acpi61.h +++ b/MdePkg/Include/IndustryStandard/Acpi61.h @@ -1979,6 +1979,8 @@ typedef struct { #define EFI_ACPI_6_1_EINJ_EXECUTE_OPERATION 0x05
#define EFI_ACPI_6_1_EINJ_CHECK_BUSY_STATUS 0x06
#define EFI_ACPI_6_1_EINJ_GET_COMMAND_STATUS 0x07
+#define EFI_ACPI_6_1_EINJ_SET_ERROR_TYPE_WITH_ADDRESS 0x08
+#define EFI_ACPI_6_1_EINJ_GET_EXECUTE_OPERATION_TIMINGS 0x09
#define EFI_ACPI_6_1_EINJ_TRIGGER_ERROR 0xFF
///
diff --git a/MdePkg/Include/IndustryStandard/Acpi62.h b/MdePkg/Include/IndustryStandard/Acpi62.h index 4dd3e21..711b88b 100644 --- a/MdePkg/Include/IndustryStandard/Acpi62.h +++ b/MdePkg/Include/IndustryStandard/Acpi62.h @@ -2292,6 +2292,8 @@ typedef struct { #define EFI_ACPI_6_2_EINJ_EXECUTE_OPERATION 0x05
#define EFI_ACPI_6_2_EINJ_CHECK_BUSY_STATUS 0x06
#define EFI_ACPI_6_2_EINJ_GET_COMMAND_STATUS 0x07
+#define EFI_ACPI_6_2_EINJ_SET_ERROR_TYPE_WITH_ADDRESS 0x08
+#define EFI_ACPI_6_2_EINJ_GET_EXECUTE_OPERATION_TIMINGS 0x09
#define EFI_ACPI_6_2_EINJ_TRIGGER_ERROR 0xFF
///
diff --git a/MdePkg/Include/IndustryStandard/Acpi63.h b/MdePkg/Include/IndustryStandard/Acpi63.h index 7582dcc..68798da 100644 --- a/MdePkg/Include/IndustryStandard/Acpi63.h +++ b/MdePkg/Include/IndustryStandard/Acpi63.h @@ -2252,6 +2252,8 @@ typedef struct { #define EFI_ACPI_6_3_EINJ_EXECUTE_OPERATION 0x05
#define EFI_ACPI_6_3_EINJ_CHECK_BUSY_STATUS 0x06
#define EFI_ACPI_6_3_EINJ_GET_COMMAND_STATUS 0x07
+#define EFI_ACPI_6_3_EINJ_SET_ERROR_TYPE_WITH_ADDRESS 0x08
+#define EFI_ACPI_6_3_EINJ_GET_EXECUTE_OPERATION_TIMINGS 0x09
#define EFI_ACPI_6_3_EINJ_TRIGGER_ERROR 0xFF
///
diff --git a/MdePkg/Include/IndustryStandard/Acpi64.h b/MdePkg/Include/IndustryStandard/Acpi64.h index faf069a..bbe6a3c 100644 --- a/MdePkg/Include/IndustryStandard/Acpi64.h +++ b/MdePkg/Include/IndustryStandard/Acpi64.h @@ -2335,6 +2335,8 @@ typedef struct { #define EFI_ACPI_6_4_EINJ_EXECUTE_OPERATION 0x05
#define EFI_ACPI_6_4_EINJ_CHECK_BUSY_STATUS 0x06
#define EFI_ACPI_6_4_EINJ_GET_COMMAND_STATUS 0x07
+#define EFI_ACPI_6_4_EINJ_SET_ERROR_TYPE_WITH_ADDRESS 0x08
+#define EFI_ACPI_6_4_EINJ_GET_EXECUTE_OPERATION_TIMINGS 0x09
#define EFI_ACPI_6_4_EINJ_TRIGGER_ERROR 0xFF
///
diff --git a/MdePkg/Include/IndustryStandard/Acpi65.h b/MdePkg/Include/IndustryStandard/Acpi65.h index b9616a3..62d2fac 100644 --- a/MdePkg/Include/IndustryStandard/Acpi65.h +++ b/MdePkg/Include/IndustryStandard/Acpi65.h @@ -2,7 +2,7 @@ ACPI 6.5 definitions from the ACPI Specification Revision 6.5 Aug, 2022.
Copyright (c) 2017 - 2022, Intel Corporation. All rights reserved.<BR>
- Copyright (c) 2019 - 2023, ARM Ltd. All rights reserved.<BR>
+ Copyright (c) 2019 - 2024, ARM Ltd. All rights reserved.<BR>
Copyright (c) 2023, Loongson Technology Corporation Limited. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -1057,6 +1057,26 @@ typedef struct { #define EFI_ACPI_6_5_RASF_PATROL_SCRUB_COMMAND_STOP_PATROL_SCRUBBER 0x03
///
+/// ACPI RAS2 PCC Descriptor
+///
+typedef struct {
+ UINT8 PccId;
+ UINT8 Reserved[2];
+ UINT8 RasFeatureType;
+ UINT32 Instance;
+} EFI_ACPI_RAS2_PCC_DESCRIPTOR;
+
+///
+/// ACPI RAS2 Feature Table definition.
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT16 Reserved;
+ UINT16 PccCount;
+ // EFI_ACPI_RAS2_PCC_DESCRIPTOR Descriptors[PccCount];
+} EFI_ACPI_6_5_RAS2_FEATURE_TABLE;
+
+///
/// Memory Power State Table definition.
///
typedef struct {
@@ -1621,7 +1641,7 @@ typedef struct { #define EFI_ACPI_6_5_NFIT_GUID_BYTE_ADDRESSABLE_PERSISTENT_MEMORY_REGION { 0x66F0D379, 0xB4F3, 0x4074, { 0xAC, 0x43, 0x0D, 0x33, 0x18, 0xB7, 0x8C, 0xDB }}
#define EFI_ACPI_6_5_NFIT_GUID_NVDIMM_CONTROL_REGION { 0x92F701F6, 0x13B4, 0x405D, { 0x91, 0x0B, 0x29, 0x93, 0x67, 0xE8, 0x23, 0x4C }}
#define EFI_ACPI_6_5_NFIT_GUID_NVDIMM_BLOCK_DATA_WINDOW_REGION { 0x91AF0530, 0x5D86, 0x470E, { 0xA6, 0xB0, 0x0A, 0x2D, 0xB9, 0x40, 0x82, 0x49 }}
-#define EFI_ACPI_6_5_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_DISK_REGION_VOLATILE { 0x77AB535A, 0x45FC, 0x6.5B, { 0x55, 0x60, 0xF7, 0xB2, 0x81, 0xD1, 0xF9, 0x6E }}
+#define EFI_ACPI_6_5_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_DISK_REGION_VOLATILE { 0x77AB535A, 0x45FC, 0x624B, { 0x55, 0x60, 0xF7, 0xB2, 0x81, 0xD1, 0xF9, 0x6E }}
#define EFI_ACPI_6_5_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_CD_REGION_VOLATILE { 0x3D5ABD30, 0x4175, 0x87CE, { 0x6D, 0x64, 0xD2, 0xAD, 0xE5, 0x23, 0xC4, 0xBB }}
#define EFI_ACPI_6_5_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_DISK_REGION_PERSISTENT { 0x5CEA02C9, 0x4D07, 0x69D3, { 0x26, 0x9F ,0x44, 0x96, 0xFB, 0xE0, 0x96, 0xF9 }}
#define EFI_ACPI_6_5_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_CD_REGION_PERSISTENT { 0x08018188, 0x42CD, 0xBB48, { 0x10, 0x0F, 0x53, 0x87, 0xD5, 0x3D, 0xED, 0x3D }}
@@ -1949,7 +1969,7 @@ typedef struct { ///
/// HEST Version (as defined in ACPI 6.5 spec.)
///
-#define EFI_ACPI_6_5_HARDWARE_ERROR_SOURCE_TABLE_REVISION 0x01
+#define EFI_ACPI_6_5_HARDWARE_ERROR_SOURCE_TABLE_REVISION 0x02
//
// Error Source structure types.
@@ -2419,7 +2439,7 @@ typedef struct { ///
/// EINJ Version (as defined in ACPI 6.5 spec.)
///
-#define EFI_ACPI_6_5_ERROR_INJECTION_TABLE_REVISION 0x01
+#define EFI_ACPI_6_5_ERROR_INJECTION_TABLE_REVISION 0x02
///
/// EINJ Error Injection Actions
@@ -2432,6 +2452,10 @@ typedef struct { #define EFI_ACPI_6_5_EINJ_EXECUTE_OPERATION 0x05
#define EFI_ACPI_6_5_EINJ_CHECK_BUSY_STATUS 0x06
#define EFI_ACPI_6_5_EINJ_GET_COMMAND_STATUS 0x07
+#define EFI_ACPI_6_5_EINJ_SET_ERROR_TYPE_WITH_ADDRESS 0x08
+#define EFI_ACPI_6_5_EINJ_GET_EXECUTE_OPERATION_TIMINGS 0x09
+#define EFI_ACPI_6_5_EINJ_EINJV2_SET_ERROR_TYPE 0x10
+#define EFI_ACPI_6_5_EINJ_EINJV2_GET_ERROR_TYPE 0x11
#define EFI_ACPI_6_5_EINJ_TRIGGER_ERROR 0xFF
///
@@ -2940,6 +2964,54 @@ typedef struct { #define EFI_ACPI_6_5_PHAT_FIRMWARE_HEALTH_DATA_RECORD_UNKNOWN 0x02
#define EFI_ACPI_6_5_PHAT_FIRMWARE_HEALTH_DATA_RECORD_ADVISORY 0x03
+///
+/// Reset Reason Health Record Vendor Data Entry
+///
+typedef struct {
+ GUID VendorDataID;
+ UINT16 Length;
+ UINT16 Revision;
+ // UINTN Data[];
+} EFI_ACPI_6_5_PHAT_RESET_REASON_HEALTH_RECORD_VENDOR_DATA_ENTRY;
+
+///
+/// Reset Reason Health Record Structure
+///
+typedef struct {
+ UINT8 SupportedSources;
+ UINT8 Source;
+ UINT8 SubSource;
+ UINT8 Reason;
+ UINT16 VendorCount;
+ // EFI_ACPI_6_5_PHAT_RESET_REASON_HEALTH_RECORD_VENDOR_DATA_ENTRY VendorSpecificResetReasonEntry[];
+} EFI_ACPI_6_5_PHAT_RESET_REASON_HEALTH_RECORD_STRUCTURE;
+
+#define EFI_ACPI_6_5_PHAT_RESET_REASON_HEADER_GUID { 0x7a014ce2, 0xf263, 0x4b77, { 0xb8, 0x8a, 0xe6, 0x33, 0x6b, 0x78, 0x2c, 0x14 }}
+
+#define EFI_ACPI_6_5_PHAT_RESET_REASON_SUPPORTED_SOURCES_UNKNOWN BIT0
+#define EFI_ACPI_6_5_PHAT_RESET_REASON_SUPPORTED_SOURCES_HARDWARE BIT1
+#define EFI_ACPI_6_5_PHAT_RESET_REASON_SUPPORTED_SOURCES_FIRMWARE BIT2
+#define EFI_ACPI_6_5_PHAT_RESET_REASON_SUPPORTED_SOURCES_SOFTWARE BIT3
+#define EFI_ACPI_6_5_PHAT_RESET_REASON_SUPPORTED_SOURCES_SUPERVISOR BIT4
+
+#define EFI_ACPI_6_5_PHAT_RESET_REASON_SOURCES_UNKNOWN BIT0
+#define EFI_ACPI_6_5_PHAT_RESET_REASON_SOURCES_HARDWARE BIT1
+#define EFI_ACPI_6_5_PHAT_RESET_REASON_SOURCES_FIRMWARE BIT2
+#define EFI_ACPI_6_5_PHAT_RESET_REASON_SOURCES_SOFTWARE BIT3
+#define EFI_ACPI_6_5_PHAT_RESET_REASON_SOURCES_SUPERVISOR BIT4
+
+#define EFI_ACPI_6_5_PHAT_RESET_REASON_REASON_UNKNOWN 0x00
+#define EFI_ACPI_6_5_PHAT_RESET_REASON_REASON_COLD_BOOT 0x01
+#define EFI_ACPI_6_5_PHAT_RESET_REASON_REASON_COLD_RESET 0x02
+#define EFI_ACPI_6_5_PHAT_RESET_REASON_REASON_WARM_RESET 0x03
+#define EFI_ACPI_6_5_PHAT_RESET_REASON_REASON_UPDATE 0x04
+#define EFI_ACPI_6_5_PHAT_RESET_REASON_REASON_UNEXPECTED_RESET 0x20
+#define EFI_ACPI_6_5_PHAT_RESET_REASON_REASON_FAULT 0x21
+#define EFI_ACPI_6_5_PHAT_RESET_REASON_REASON_TIMEOUT 0x22
+#define EFI_ACPI_6_5_PHAT_RESET_REASON_REASON_THERMAL 0x23
+#define EFI_ACPI_6_5_PHAT_RESET_REASON_REASON_POWER_LOSS 0x24
+#define EFI_ACPI_6_5_PHAT_RESET_REASON_REASON_POWER_BUTTON 0x25
+
//
// Known table signatures
//
@@ -3070,6 +3142,11 @@ typedef struct { #define EFI_ACPI_6_5_PERSISTENT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('P', 'S', 'D', 'T')
///
+/// "RAS2" ACPI RAS2 Feature Table
+///
+#define EFI_ACPI_6_5_ACPI_RAS2_FEATURE_TABLE_SIGNATURE SIGNATURE_32('R', 'A', 'S', '2')
+
+///
/// "RASF" ACPI RAS Feature Table
///
#define EFI_ACPI_6_5_ACPI_RAS_FEATURE_TABLE_SIGNATURE SIGNATURE_32('R', 'A', 'S', 'F')
@@ -3264,6 +3341,11 @@ typedef struct { ///
#define EFI_ACPI_6_5_XEN_PROJECT_TABLE_SIGNATURE SIGNATURE_32('X', 'E', 'N', 'V')
+///
+/// "MPAM" Memory System Resource Partitioning and Monitoring Table
+///
+#define EFI_ACPI_MEMORY_SYSTEM_RESOURCE_PARTITIONING_AND_MONITORING_TABLE_SIGNATURE SIGNATURE_32('M', 'P', 'A', 'M')
+
#pragma pack()
#endif
diff --git a/MdePkg/Include/IndustryStandard/Http11.h b/MdePkg/Include/IndustryStandard/Http11.h index 2137ef1..7636a9e 100644 --- a/MdePkg/Include/IndustryStandard/Http11.h +++ b/MdePkg/Include/IndustryStandard/Http11.h @@ -248,6 +248,34 @@ ///
#define HTTP_EXPECT_100_CONTINUE "100-continue"
+///
+/// Content-Range Response Header
+/// The Content-Range response HTTP header indicates where in a
+/// full body message a partial message belongs.
+///
+#define HTTP_HEADER_CONTENT_RANGE "Content-Range"
+
+///
+/// Last-Modified Response Header
+/// The Last-Modified response HTTP header contains a date and time when
+/// the origin server believes the resource was last modified. It is used
+/// as a validator to determine if the resource is the same as the
+/// previously stored one. Less accurate than an ETag header,
+/// it is a fallback mechanism. Conditional requests containing
+/// If-Modified-Since or If-Unmodified-Since headers make use of this field.
+///
+#define HTTP_HEADER_LAST_MODIFIED "Last-Modified"
+
+///
+/// If Unmodified Since Request Header
+/// Makes the request for the resource conditional: the server will send
+/// the requested resource or accept it in the case of a POST or another
+/// non-safe method only if the resource has not been modified after the
+/// date specified by this HTTP header. If the resource has been modified
+/// after the specified date, the response will be a 412 Precondition Failed error.
+///
+#define HTTP_HEADER_IF_UNMODIFIED_SINCE "If-Unmodified-Since"
+
#pragma pack()
#endif
diff --git a/MdePkg/Include/IndustryStandard/IoRemappingTable.h b/MdePkg/Include/IndustryStandard/IoRemappingTable.h index 544aa67..851ce00 100644 --- a/MdePkg/Include/IndustryStandard/IoRemappingTable.h +++ b/MdePkg/Include/IndustryStandard/IoRemappingTable.h @@ -43,8 +43,9 @@ #define EFI_ACPI_IORT_MEM_ACCESS_PROP_AH_RA BIT2
#define EFI_ACPI_IORT_MEM_ACCESS_PROP_AH_AHO BIT3
-#define EFI_ACPI_IORT_MEM_ACCESS_FLAGS_CPM BIT0
-#define EFI_ACPI_IORT_MEM_ACCESS_FLAGS_DACS BIT1
+#define EFI_ACPI_IORT_MEM_ACCESS_FLAGS_CPM BIT0
+#define EFI_ACPI_IORT_MEM_ACCESS_FLAGS_DACS BIT1
+#define EFI_ACPI_IORT_MEM_ACCESS_FLAGS_CANWBS BIT2
#define EFI_ACPI_IORT_SMMUv1v2_MODEL_v1 0x0
#define EFI_ACPI_IORT_SMMUv1v2_MODEL_v2 0x1
@@ -60,7 +61,8 @@ #define EFI_ACPI_IORT_SMMUv1v2_INT_FLAG_EDGE 0x1
#define EFI_ACPI_IORT_SMMUv3_FLAG_COHAC_OVERRIDE BIT0
-#define EFI_ACPI_IORT_SMMUv3_FLAG_HTTU_OVERRIDE BIT1
+#define EFI_ACPI_IORT_SMMUv3_FLAG_HTTU_OVERRIDE BIT1 // HW update of Access Flag supported
+#define EFI_ACPI_IORT_SMMUv3_FLAG_HTTU_OVERRIDE_DS BIT2 // HW update of Access Flag + Dirty Flag supported
#define EFI_ACPI_IORT_SMMUv3_FLAG_PROXIMITY_DOMAIN BIT3
#define EFI_ACPI_IORT_SMMUv3_FLAG_DEVICEID_VALID BIT4
diff --git a/MdePkg/Include/IndustryStandard/IpmiNetFnGroupExtension.h b/MdePkg/Include/IndustryStandard/IpmiNetFnGroupExtension.h index 6b26656..b821ad5 100644 --- a/MdePkg/Include/IndustryStandard/IpmiNetFnGroupExtension.h +++ b/MdePkg/Include/IndustryStandard/IpmiNetFnGroupExtension.h @@ -2,12 +2,21 @@ IPMI 2.0 definitions from the IPMI Specification Version 2.0, Revision 1.1.
Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2024, Ampere Computing LLC. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ - Arm Server Base Manageability Requirements (SBMR) Specification
+ Revision 2.0d, Section F
+ https://developer.arm.com/documentation/den0069
+
**/
#ifndef _IPMI_NET_FN_GROUP_EXTENSION_H_
#define _IPMI_NET_FN_GROUP_EXTENSION_H_
+#include <Pi/PiStatusCode.h>
+
//
// Net function definition for Group Extension command
//
@@ -17,4 +26,72 @@ // All Group Extension commands and their structure definitions to follow here
//
+///
+/// Constants and structure definitions for Boot Progress Codes
+///
+/// See Section F of the Arm Server Base Manageability Requirements 2.0 specification,
+/// https://developer.arm.com/documentation/den0069
+///
+
+#pragma pack(1)
+//
+// Definitions for send progress code command
+//
+#define IPMI_GROUP_EXTENSION_BOOT_PROGRESS_CODE_SEND 0x02
+
+//
+// Definitions for get progress code command
+//
+#define IPMI_GROUP_EXTENSION_BOOT_PROGRESS_CODE_GET 0x03
+
+//
+// Definitions for send and get progress code command response
+//
+#define IPMI_GROUP_EXTENSION_BOOT_PROGRESS_CODE_COMPLETED_NORMALLY 0x00
+#define IPMI_GROUP_EXTENSION_BOOT_PROGRESS_CODE_COMPLETED_ERROR 0x80
+#define IPMI_GROUP_EXTENSION_BOOT_PROGRESS_CODE_DEFINING_BODY 0xAE
+
+//
+// Structure for the format of the boot progress code data
+// See Table 29: SBMR Boot Progress Codes format
+//
+typedef struct {
+ EFI_STATUS_CODE_TYPE CodeType;
+ EFI_STATUS_CODE_VALUE CodeValue;
+ UINT8 Instance;
+} IPMI_GROUP_EXTENSION_BOOT_PROGRESS_CODE_FORMAT;
+
+//
+// Structure for the boot progress code send request
+//
+typedef struct {
+ UINT8 DefiningBody;
+ IPMI_GROUP_EXTENSION_BOOT_PROGRESS_CODE_FORMAT BootProgressCode;
+} IPMI_GROUP_EXTENSION_BOOT_PROGRESS_CODE_SEND_REQUEST;
+
+//
+// Structure for the boot progress code send response
+//
+typedef struct {
+ UINT8 CompletionCode;
+ UINT8 DefiningBody;
+} IPMI_GROUP_EXTENSION_BOOT_PROGRESS_CODE_SEND_RESPONSE;
+
+//
+// Structure for the boot progress code get request
+//
+typedef struct {
+ UINT8 DefiningBody;
+} IPMI_GROUP_EXTENSION_BOOT_PROGRESS_CODE_GET_REQUEST;
+
+//
+// Structure for the boot progress code get response
+//
+typedef struct {
+ UINT8 CompletionCode;
+ UINT8 DefiningBody;
+ IPMI_GROUP_EXTENSION_BOOT_PROGRESS_CODE_FORMAT BootProgressCode;
+} IPMI_GROUP_EXTENSION_BOOT_PROGRESS_CODE_GET_RESPONSE;
+#pragma pack()
+
#endif
diff --git a/MdePkg/Include/IndustryStandard/Mpam.h b/MdePkg/Include/IndustryStandard/Mpam.h new file mode 100644 index 0000000..8358b35 --- /dev/null +++ b/MdePkg/Include/IndustryStandard/Mpam.h @@ -0,0 +1,246 @@ +/** @file
+ ACPI for Memory System Resource Partitioning and Monitoring 2.0 (MPAM) as
+ specified in ARM spec DEN0065
+
+ Copyright (c) 2024, Arm Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Specification Reference:
+ - [1] ACPI for Memory System Resource Partitioning and Monitoring 2.0
+ (https://developer.arm.com/documentation/den0065/latest)
+
+ @par Glossary:
+ - MPAM - Memory System Resource Partitioning And Monitoring
+ - MSC - Memory System Component
+ - PCC - Platform Communication Channel
+ - RIS - Resource Instance Selection
+ - SMMU - Arm System Memory Management Unit
+ **/
+
+#ifndef MPAM_H_
+#define MPAM_H_
+
+#include <IndustryStandard/Acpi.h>
+
+///
+/// MPAM Revision
+///
+#define EFI_ACPI_MEMORY_SYSTEM_RESOURCE_PARTITIONING_AND_MONITORING_TABLE_REVISION (0x01)
+
+///
+/// MPAM Interrupt mode
+///
+#define EFI_ACPI_MPAM_INTERRUPT_LEVEL_TRIGGERED (0x0)
+#define EFI_ACPI_MPAM_INTERRUPT_EDGE_TRIGGERED (0x1)
+
+///
+/// MPAM Interrupt type
+///
+#define EFI_ACPI_MPAM_INTERRUPT_WIRED (0x0)
+
+///
+/// MPAM Interrupt affinity type
+///
+#define EFI_ACPI_MPAM_INTERRUPT_PROCESSOR_AFFINITY (0x0)
+#define EFI_ACPI_MPAM_INTERRUPT_PROCESSOR_CONTAINER_AFFINITY (0x1)
+
+///
+/// MPAM MSC affinity valid
+///
+#define EFI_ACPI_MPAM_INTERRUPT_AFFINITY_NOT_VALID (0x0)
+#define EFI_ACPI_MPAM_INTERRUPT_AFFINITY_VALID (0x1)
+
+///
+/// MPAM Interrupt flag - bit positions
+///
+#define EFI_ACPI_MPAM_INTERRUPT_MODE_SHIFT (0)
+#define EFI_ACPI_MPAM_INTERRUPT_TYPE_SHIFT (1)
+#define EFI_ACPI_MPAM_INTERRUPT_AFFINITY_TYPE_SHIFT (3)
+#define EFI_ACPI_MPAM_INTERRUPT_AFFINITY_VALID_SHIFT (4)
+#define EFI_ACPI_MPAM_INTERRUPT_RESERVED_SHIFT (5)
+
+///
+/// MPAM Interrupt flag - bit masks
+///
+#define EFI_ACPI_MPAM_INTERRUPT_MODE_MASK (0x1)
+#define EFI_ACPI_MPAM_INTERRUPT_TYPE_MASK (0x3)
+#define EFI_ACPI_MPAM_INTERRUPT_AFFINITY_TYPE_MASK (0x8)
+#define EFI_ACPI_MPAM_INTERRUPT_AFFINITY_VALID_MASK (0x10)
+#define EFI_ACPI_MPAM_INTERRUPT_RESERVED_MASK (0xFFFFFFE0)
+
+///
+/// MPAM Location types
+/// as described in document [1], table 11.
+///
+#define EFI_ACPI_MPAM_LOCATION_PROCESSOR_CACHE (0x0)
+#define EFI_ACPI_MPAM_LOCATION_MEMORY (0x1)
+#define EFI_ACPI_MPAM_LOCATION_SMMU (0x2)
+#define EFI_ACPI_MPAM_LOCATION_MEMORY_CACHE (0x3)
+#define EFI_ACPI_MPAM_LOCATION_ACPI_DEVICE (0x4)
+#define EFI_ACPI_MPAM_LOCATION_INTERCONNECT (0x5)
+#define EFI_ACPI_MPAM_LOCATION_UNKNOWN (0xFF)
+
+///
+/// MPAM Interface types
+/// as desscribed in document[1], table 4.
+///
+#define EFI_ACPI_MPAM_INTERFACE_MMIO (0x00)
+#define EFI_ACPI_MPAM_INTERFACE_PCC (0x0A)
+
+///
+/// MPAM Link types
+/// as described in document [1], table 19.
+///
+#define EFI_ACPI_MPAM_LINK_TYPE_NUMA (0x00)
+#define EFI_ACPI_MPAM_LINK_TYPE_PROC (0x01)
+
+#pragma pack(1)
+
+///
+/// MPAM MSC generic locator descriptor
+/// as described in document [1], table 12.
+///
+typedef struct {
+ UINT64 Descriptor1;
+ UINT32 Descriptor2;
+} EFI_ACPI_MPAM_GENERIC_LOCATOR;
+
+///
+/// MPAM processor cache locator descriptor
+/// as described in document [1], table 13.
+///
+typedef struct {
+ UINT64 CacheReference;
+ UINT32 Reserved;
+} EFI_ACPI_MPAM_CACHE_LOCATOR;
+
+///
+/// MPAM memory locator descriptor
+/// as described in document [1], table 14.
+///
+typedef struct {
+ UINT64 ProximityDomain;
+ UINT32 Reserved;
+} EFI_ACPI_MPAM_MEMORY_LOCATOR;
+
+///
+/// MPAM SMMU locator descriptor
+/// as described in document [1], table 15.
+///
+typedef struct {
+ UINT64 SmmuInterface;
+ UINT32 Reserved;
+} EFI_ACPI_MPAM_SMMU_LOCATOR;
+
+///
+/// MPAM memory-side cache locator descriptor
+/// as described in Document [1], table 16.
+///
+typedef struct {
+ UINT8 Reserved[7];
+ UINT8 Level;
+ UINT32 Reference;
+} EFI_ACPI_MPAM_MEMORY_CACHE_LOCATOR;
+
+///
+/// MPAM ACPI device locator descriptor
+/// as described in document [1], table 17.
+///
+typedef struct {
+ UINT64 AcpiHardwareId;
+ UINT32 AcpiUniqueId;
+} EFI_ACPI_MPAM_ACPI_LOCATOR;
+
+///
+/// MPAM interconnect locator descriptor
+/// as described in document [1], table 18.
+///
+typedef struct {
+ UINT64 InterconnectDescTblOff;
+ UINT32 Reserved;
+} EFI_ACPI_MPAM_INTERCONNECT_LOCATOR;
+
+///
+/// MPAM interconnect descriptor
+/// as described in document [1], table 19.
+///
+typedef struct {
+ UINT32 SourceId;
+ UINT32 DestinationId;
+ UINT8 LinkType;
+ UINT8 Reserved[3];
+} EFI_ACPI_MPAM_INTERCONNECT_DESCRIPTOR;
+
+///
+/// MPAM interconnect descriptor table
+/// as described in document [1], table 20.
+///
+typedef struct {
+ UINT8 Signature[16];
+ UINT32 NumDescriptors;
+} EFI_ACPI_MPAM_INTERCONNECT_DESCRIPTOR_TABLE;
+
+///
+/// MPAM resource locator
+///
+typedef union {
+ EFI_ACPI_MPAM_CACHE_LOCATOR CacheLocator;
+ EFI_ACPI_MPAM_MEMORY_LOCATOR MemoryLocator;
+ EFI_ACPI_MPAM_SMMU_LOCATOR SmmuLocator;
+ EFI_ACPI_MPAM_MEMORY_CACHE_LOCATOR MemCacheLocator;
+ EFI_ACPI_MPAM_ACPI_LOCATOR AcpiLocator;
+ EFI_ACPI_MPAM_INTERCONNECT_LOCATOR InterconnectIfcLocator;
+ EFI_ACPI_MPAM_GENERIC_LOCATOR GenericLocator;
+} EFI_ACPI_MPAM_LOCATOR;
+
+///
+/// MPAM MSC node body
+/// as described document [1], table 4.
+///
+typedef struct {
+ UINT16 Length;
+ UINT8 InterfaceType;
+ UINT8 Reserved;
+ UINT32 Identifier;
+ UINT64 BaseAddress;
+ UINT32 MmioSize;
+ UINT32 OverflowInterrupt;
+ UINT32 OverflowInterruptFlags;
+ UINT32 Reserved1;
+ UINT32 OverflowInterruptAffinity;
+ UINT32 ErrorInterrupt;
+ UINT32 ErrorInterruptFlags;
+ UINT32 Reserved2;
+ UINT32 ErrorInterruptAffinity;
+ UINT32 MaxNrdyUsec;
+ UINT64 HardwareIdLinkedDevice;
+ UINT32 InstanceIdLinkedDevice;
+ UINT32 NumResources;
+} EFI_ACPI_MPAM_MSC_NODE;
+
+///
+/// MPAM MSC resource
+/// as described in document [1], table 9.
+///
+typedef struct {
+ UINT32 Identifier;
+ UINT8 RisIndex;
+ UINT16 Reserved1;
+ UINT8 LocatorType;
+ EFI_ACPI_MPAM_LOCATOR Locator;
+ UINT32 NumFunctionalDependencies;
+} EFI_ACPI_MPAM_MSC_RESOURCE;
+
+///
+/// MPAM Function dependency descriptor
+/// as described in document [1], table 10.
+///
+typedef struct {
+ UINT32 Producer;
+ UINT32 Reserved;
+} EFI_ACPI_MPAM_FUNCTIONAL_DEPENDENCY_DESCRIPTOR;
+
+#pragma pack()
+
+#endif
diff --git a/MdePkg/Include/IndustryStandard/Nvme.h b/MdePkg/Include/IndustryStandard/Nvme.h index 2a94e21..ffb8b84 100644 --- a/MdePkg/Include/IndustryStandard/Nvme.h +++ b/MdePkg/Include/IndustryStandard/Nvme.h @@ -3,6 +3,7 @@ (C) Copyright 2016 Hewlett Packard Enterprise Development LP<BR>
Copyright (c) 2017 - 2023, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) Microsoft Corporation.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@par Specification Reference:
@@ -27,10 +28,12 @@ #define NVME_INTMC_OFFSET 0x0010 // Interrupt Mask Clear
#define NVME_CC_OFFSET 0x0014 // Controller Configuration
#define NVME_CSTS_OFFSET 0x001c // Controller Status
-#define NVME_NSSR_OFFSET 0x0020 // NVM Subsystem Reset
+#define NVME_NSSR_OFFSET 0x0020 // NVM Subsystem Reset (Optional)
#define NVME_AQA_OFFSET 0x0024 // Admin Queue Attributes
#define NVME_ASQ_OFFSET 0x0028 // Admin Submission Queue Base Address
#define NVME_ACQ_OFFSET 0x0030 // Admin Completion Queue Base Address
+#define NVME_CMBLOC_OFFSET 0x0038 // Control Memory Buffer Location (Optional)
+#define NVME_CMBSZ_OFFSET 0x003C // Control Memory Buffer Size (Optional)
#define NVME_BPINFO_OFFSET 0x0040 // Boot Partition Information
#define NVME_BPRSEL_OFFSET 0x0044 // Boot Partition Read Select
#define NVME_BPMBL_OFFSET 0x0048 // Boot Partition Memory Buffer Location
@@ -382,7 +385,21 @@ typedef struct { UINT8 Cmic; /* Multi-interface Capabilities */
UINT8 Mdts; /* Maximum Data Transfer Size */
UINT8 Cntlid[2]; /* Controller ID */
- UINT8 Rsvd1[176]; /* Reserved as of Nvm Express 1.1 Spec */
+ UINT32 Ver; /* Version */
+ UINT32 Rtd3r; /* RTD3 Resume Latency */
+ UINT32 Rtd3e; /* RTD3 Entry Latency */
+ UINT32 Oaes; /* Optional Async Events Supported */
+ UINT32 Ctratt; /* Controller Attributes */
+ UINT16 Rrls; /* Read Recovery Levels Supported */
+ UINT8 Rsvd1[9]; /* Reserved as of NVM Express 1.4c Spec */
+ UINT8 Cntrltype; /* Controller Type */
+ UINT8 Fguid[16]; /* FRU Globally Unique Identifier */
+ UINT16 Crdt1; /* Command Retry Delay Time 1 */
+ UINT16 Crdt2; /* Command Retry Delay Time 2 */
+ UINT16 Crdt3; /* Command Retry Delay Time 3 */
+ UINT8 Rsvd2[106]; /* Reserved as of NVM Express 1.4c Spec */
+ UINT8 Rsvd3[16]; /* Reserved for NVMe MI Spec */
+
//
// Admin Command Set Attributes
//
@@ -418,30 +435,39 @@ typedef struct { UINT16 Mntmt; /* Minimum Thermal Management Temperature */
UINT16 Mxtmt; /* Maximum Thermal Management Temperature */
NVME_SANICAP Sanicap; /* Sanitize Capabilities */
- UINT8 Rsvd2[180]; /* Reserved as of Nvm Express 1.4 Spec */
+ UINT32 Hmminds; /* Host Memory Buffer Minimum Descriptor Entry Size */
+ UINT16 Hmmaxd; /* Host Memory Maximum Descriptors Entries */
+ UINT16 Nsetidmax; /* NVM Set Identifier Maximum */
+ UINT16 Endgidmax; /* Endurance Group Identifier Maximum */
+ UINT8 Anatt; /* ANA Transition Time */
+ UINT8 Anacap; /* Asymmetric Namespace Access Capabilities */
+ UINT32 Anagrpmax; /* ANA Group Identifier Maximum */
+ UINT32 Nanagrpid; /* Number of ANA Group Identifiers */
+ UINT32 Pels; /* Persistent Event Log Size */
+ UINT8 Rsvd4[156]; /* Reserved as of NVM Express 1.4c Spec */
//
// NVM Command Set Attributes
//
- UINT8 Sqes; /* Submission Queue Entry Size */
- UINT8 Cqes; /* Completion Queue Entry Size */
- UINT16 Rsvd3; /* Reserved as of Nvm Express 1.1 Spec */
- UINT32 Nn; /* Number of Namespaces */
- UINT16 Oncs; /* Optional NVM Command Support */
- UINT16 Fuses; /* Fused Operation Support */
- UINT8 Fna; /* Format NVM Attributes */
- UINT8 Vwc; /* Volatile Write Cache */
- UINT16 Awun; /* Atomic Write Unit Normal */
- UINT16 Awupf; /* Atomic Write Unit Power Fail */
- UINT8 Nvscc; /* NVM Vendor Specific Command Configuration */
- UINT8 Rsvd4; /* Reserved as of Nvm Express 1.1 Spec */
- UINT16 Acwu; /* Atomic Compare & Write Unit */
- UINT16 Rsvd5; /* Reserved as of Nvm Express 1.1 Spec */
- UINT32 Sgls; /* SGL Support */
- UINT8 Rsvd6[164]; /* Reserved as of Nvm Express 1.1 Spec */
- //
- // I/O Command set Attributes
- //
- UINT8 Rsvd7[1344]; /* Reserved as of Nvm Express 1.1 Spec */
+ UINT8 Sqes; /* Submission Queue Entry Size */
+ UINT8 Cqes; /* Completion Queue Entry Size */
+ UINT16 Maxcmd; /* Maximum Outstanding Commands */
+ UINT32 Nn; /* Number of Namespaces */
+ UINT16 Oncs; /* Optional NVM Command Support */
+ UINT16 Fuses; /* Fused Operation Support */
+ UINT8 Fna; /* Format NVM Attributes */
+ UINT8 Vwc; /* Volatile Write Cache */
+ UINT16 Awun; /* Atomic Write Unit Normal */
+ UINT16 Awupf; /* Atomic Write Unit Power Fail */
+ UINT8 Nvscc; /* NVM Vendor Specific Command Configuration */
+ UINT8 Nwpc; /* Namespace Write Protection Capabilities */
+ UINT16 Acwu; /* Atomic Compare & Write Unit */
+ UINT16 Rsvd5; /* Reserved as of NVM Express 1.4c Spec */
+ UINT32 Sgls; /* SGL Support */
+ UINT32 Mnan; /* Maximum Number of Allowed Namespace */
+ UINT8 Rsvd6[224]; /* Reserved as of NVM Express 1.4c Spec */
+ UINT8 Subnqn[256]; /* NVM Subsystem NVMe Qualified Name */
+ UINT8 Rsvd7[768]; /* Reserved as of NVM Express 1.4c Spec */
+ UINT8 Rsvd8[256]; /* Reserved for NVMe over Fabrics Spec */
//
// Power State Descriptors
//
@@ -764,6 +790,10 @@ typedef struct { UINT32 Rsvd1 : 20;
} NVME_ADMIN_FORMAT_NVM;
+#define SES_NO_SECURE_ERASE 0x0
+#define SES_USER_DATA_ERASE 0x1
+#define SES_CRYPTO_ERASE 0x2
+
//
// NvmExpress Admin Security Receive Command
//
diff --git a/MdePkg/Include/IndustryStandard/Pci.h b/MdePkg/Include/IndustryStandard/Pci.h index 42c00ac..4220ad8 100644 --- a/MdePkg/Include/IndustryStandard/Pci.h +++ b/MdePkg/Include/IndustryStandard/Pci.h @@ -9,7 +9,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #ifndef _PCI_H_
#define _PCI_H_
-#include <IndustryStandard/PciExpress50.h>
+#include <IndustryStandard/PciExpress60.h>
#include <IndustryStandard/PciCodeId.h>
#endif
diff --git a/MdePkg/Include/IndustryStandard/PciExpress21.h b/MdePkg/Include/IndustryStandard/PciExpress21.h index 341e3e5..b437ca5 100644 --- a/MdePkg/Include/IndustryStandard/PciExpress21.h +++ b/MdePkg/Include/IndustryStandard/PciExpress21.h @@ -40,7 +40,7 @@ typedef union { UINT16 SlotImplemented : 1;
UINT16 InterruptMessageNumber : 5;
UINT16 Undefined : 1;
- UINT16 Reserved : 1;
+ UINT16 FlitModeSupported : 1;
} Bits;
UINT16 Uint16;
} PCI_REG_PCIE_CAPABILITY;
@@ -64,11 +64,13 @@ typedef union { UINT32 EndpointL1AcceptableLatency : 3;
UINT32 Undefined : 3;
UINT32 RoleBasedErrorReporting : 1;
- UINT32 Reserved : 2;
+ UINT32 ErrCorSubclassCapable : 1;
+ UINT32 RxMpsFixed : 1;
UINT32 CapturedSlotPowerLimitValue : 8;
UINT32 CapturedSlotPowerLimitScale : 2;
UINT32 FunctionLevelReset : 1;
- UINT32 Reserved2 : 3;
+ UINT32 MixedMpsSupported : 1;
+ UINT32 Reserved2 : 2;
} Bits;
UINT32 Uint32;
} PCI_REG_PCIE_DEVICE_CAPABILITY;
@@ -111,13 +113,14 @@ typedef union { typedef union {
struct {
- UINT16 CorrectableError : 1;
- UINT16 NonFatalError : 1;
- UINT16 FatalError : 1;
- UINT16 UnsupportedRequest : 1;
- UINT16 AuxPower : 1;
- UINT16 TransactionsPending : 1;
- UINT16 Reserved : 10;
+ UINT16 CorrectableError : 1;
+ UINT16 NonFatalError : 1;
+ UINT16 FatalError : 1;
+ UINT16 UnsupportedRequest : 1;
+ UINT16 AuxPower : 1;
+ UINT16 TransactionsPending : 1;
+ UINT16 EmergencyPowerReductionDetected : 1;
+ UINT16 Reserved : 9;
} Bits;
UINT16 Uint16;
} PCI_REG_PCIE_DEVICE_STATUS;
@@ -146,7 +149,7 @@ typedef union { typedef union {
struct {
UINT16 AspmControl : 2;
- UINT16 Reserved : 1;
+ UINT16 PtmPropagationDelayB : 1;
UINT16 ReadCompletionBoundary : 1;
UINT16 LinkDisable : 1;
UINT16 RetrainLink : 1;
@@ -156,6 +159,9 @@ typedef union { UINT16 HardwareAutonomousWidthDisable : 1;
UINT16 LinkBandwidthManagementInterrupt : 1;
UINT16 LinkAutonomousBandwidthInterrupt : 1;
+ UINT16 SrisClocking : 1;
+ UINT16 FlitModeDisable : 1;
+ UINT16 DrsSignalingControl : 2;
} Bits;
UINT16 Uint16;
} PCI_REG_PCIE_LINK_CONTROL;
@@ -205,7 +211,9 @@ typedef union { UINT16 PowerController : 1;
UINT16 ElectromechanicalInterlock : 1;
UINT16 DataLinkLayerStateChanged : 1;
- UINT16 Reserved : 3;
+ UINT16 AutoSlotPowerLimitDisable : 1;
+ UINT16 InbandPdDisable : 1;
+ UINT16 Reserved : 1;
} Bits;
UINT16 Uint16;
} PCI_REG_PCIE_SLOT_CONTROL;
@@ -233,7 +241,8 @@ typedef union { UINT16 SystemErrorOnFatalError : 1;
UINT16 PmeInterrupt : 1;
UINT16 CrsSoftwareVisibility : 1;
- UINT16 Reserved : 11;
+ UINT16 NoNfmSubtree : 1;
+ UINT16 Reserved : 10;
} Bits;
UINT16 Uint16;
} PCI_REG_PCIE_ROOT_CONTROL;
@@ -268,7 +277,7 @@ typedef union { UINT32 NoRoEnabledPrPrPassing : 1;
UINT32 LtrMechanism : 1;
UINT32 TphCompleter : 2;
- UINT32 LnSystemCLS : 2;
+ UINT32 Reserved : 2;
UINT32 TenBitTagCompleterSupported : 1;
UINT32 TenBitTagRequesterSupported : 1;
UINT32 Obff : 2;
@@ -277,7 +286,9 @@ typedef union { UINT32 MaxEndEndTlpPrefixes : 2;
UINT32 EmergencyPowerReductionSupported : 2;
UINT32 EmergencyPowerReductionInitializationRequired : 1;
- UINT32 Reserved3 : 4;
+ UINT32 Reserved2 : 1;
+ UINT32 DmwrCompleter : 1;
+ UINT32 DmwrLengths : 2;
UINT32 FrsSupported : 1;
} Bits;
UINT32 Uint32;
@@ -330,10 +341,15 @@ typedef union { typedef union {
struct {
- UINT32 Reserved : 1;
- UINT32 LinkSpeedsVector : 7;
- UINT32 Crosslink : 1;
- UINT32 Reserved2 : 23;
+ UINT32 Reserved : 1;
+ UINT32 LinkSpeedsVector : 7;
+ UINT32 Crosslink : 1;
+ UINT32 LowerSkpOsGeneration : 7;
+ UINT32 LowerSkpOsReception : 7;
+ UINT32 RetimerPresenceDetect : 1;
+ UINT32 TwoRetimersPresenceDetect : 1;
+ UINT32 Reserved2 : 6;
+ UINT32 DrsSupported : 1;
} Bits;
UINT32 Uint32;
} PCI_REG_PCIE_LINK_CAPABILITY2;
@@ -360,11 +376,25 @@ typedef union { UINT16 EqualizationPhase2Successful : 1;
UINT16 EqualizationPhase3Successful : 1;
UINT16 LinkEqualizationRequest : 1;
- UINT16 Reserved : 10;
+ UINT16 RetimerPresence : 1;
+ UINT16 TwoRetimersPresence : 1;
+ UINT16 CrosslinkResolution : 2;
+ UINT16 FlitModeStatus : 1;
+ UINT16 Reserved : 1;
+ UINT16 DownstreamComponentPresence : 3;
+ UINT16 DRSMessageReceived : 1;
} Bits;
UINT16 Uint16;
} PCI_REG_PCIE_LINK_STATUS2;
+typedef union {
+ struct {
+ UINT32 InbandPdDisable : 1;
+ UINT32 Reserved : 30;
+ } Bits;
+ UINT32 Uint32;
+} PCI_REG_PCIE_SLOT_CAPABILITY2;
+
typedef struct {
EFI_PCI_CAPABILITY_HDR Hdr;
PCI_REG_PCIE_CAPABILITY Capability;
@@ -386,7 +416,7 @@ typedef struct { PCI_REG_PCIE_LINK_CAPABILITY2 LinkCapability2;
PCI_REG_PCIE_LINK_CONTROL2 LinkControl2;
PCI_REG_PCIE_LINK_STATUS2 LinkStatus2;
- UINT32 SlotCapability2;
+ PCI_REG_PCIE_SLOT_CAPABILITY2 SlotCapability2;
UINT16 SlotControl2;
UINT16 SlotStatus2;
} PCI_CAPABILITY_PCIEXP;
diff --git a/MdePkg/Include/IndustryStandard/PciExpress60.h b/MdePkg/Include/IndustryStandard/PciExpress60.h new file mode 100644 index 0000000..5427ddd --- /dev/null +++ b/MdePkg/Include/IndustryStandard/PciExpress60.h @@ -0,0 +1,121 @@ +/** @file
+Support for the PCI Express 6.0 standard.
+
+This header file may not define all structures. Please extend as required.
+
+Copyright (c) 2024, American Megatrends International LLC. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef PCIEXPRESS60_H_
+#define PCIEXPRESS60_H_
+
+#include <IndustryStandard/PciExpress50.h>
+
+/// The Physical Layer PCI Express Extended Capability definitions.
+///
+/// Based on section 7.7.7 of PCI Express Base Specification 6.0.
+///@{
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_PHYSICAL_LAYER_64_0_ID 0x0031
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_PHYSICAL_LAYER_64_0_VER1 0x1
+
+// Register offsets from Physical Layer PCI-E Ext Cap Header
+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_64_0_CAPABILITIES_OFFSET 0x04
+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_64_0_CONTROL_OFFSET 0x08
+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_64_0_STATUS_OFFSET 0x0C
+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_64_0_LANE_EQUALIZATION_CONTROL_OFFSET 0x10
+
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_DEVICE3_ID 0x002F
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_DEVICE3_VER1 0x1
+
+#define EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_3_OFFSET 0x04
+#define EFI_PCIE_CAPABILITY_DEVICE_CONTROL_3_OFFSET 0x08
+#define EFI_PCIE_CAPABILITY_DEVICE_STATUS_3_OFFSET 0x0C
+
+#pragma pack(1)
+
+typedef union {
+ struct {
+ UINT32 Reserved : 32; // Reserved bit 0:31
+ } Bits;
+ UINT32 Uint32;
+} PCI_EXPRESS_REG_PHYSICAL_LAYER_64_0_CAPABILITIES;
+
+typedef union {
+ struct {
+ UINT32 Reserved : 32; // Reserved bit 0:31
+ } Bits;
+ UINT32 Uint32;
+} PCI_EXPRESS_REG_PHYSICAL_LAYER_64_0_CONTROL;
+
+typedef union {
+ struct {
+ UINT32 EqualizationComplete : 1; // bit 0
+ UINT32 EqualizationPhase1Success : 1; // bit 1
+ UINT32 EqualizationPhase2Success : 1; // bit 2
+ UINT32 EqualizationPhase3Success : 1; // bit 3
+ UINT32 LinkEqualizationRequest : 1; // bit 4
+ UINT32 TransmitterPrecodingOn : 1; // bit 5
+ UINT32 TransmitterPrecodeRequest : 1; // bit 6
+ UINT32 NoEqualizationNeededRcvd : 1; // bit 7
+ UINT32 Reserved : 24; // Reserved bit 8:31
+ } Bits;
+ UINT32 Uint32;
+} PCI_EXPRESS_REG_PHYSICAL_LAYER_64_0_STATUS;
+
+typedef union {
+ struct {
+ UINT8 DownstreamPortTransmitterPreset : 4; // bit 0..3
+ UINT8 UpstreamPortTransmitterPreset : 4; // bit 4..7
+ } Bits;
+ UINT8 Uint8;
+} PCI_EXPRESS_REG_PHYSICAL_LAYER_64_0_LANE_EQUALIZATION_CONTROL;
+
+typedef struct {
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
+ PCI_EXPRESS_REG_PHYSICAL_LAYER_64_0_CAPABILITIES Capablities;
+ PCI_EXPRESS_REG_PHYSICAL_LAYER_64_0_CONTROL Control;
+ PCI_EXPRESS_REG_PHYSICAL_LAYER_64_0_STATUS Status;
+ PCI_EXPRESS_REG_PHYSICAL_LAYER_64_0_LANE_EQUALIZATION_CONTROL LaneEqualizationControl[1];
+} PCI_EXPRESS_EXTENDED_CAPABILITIES_PHYSICAL_LAYER_64_0;
+///@}
+
+typedef union {
+ struct {
+ UINT32 DmwrRequestRouting : 1; // bit 0
+ UINT32 FourteenBitTagCompleter : 1; // bit 1
+ UINT32 FourteenBitTagRequester : 1; // bit 2
+ UINT32 ReceiverL0p : 1; // bit 3
+ UINT32 PortL0pExitLatencyLatency : 3; // bit 4..6
+ UINT32 RetimerL0pExit : 3; // bit 7..9
+ UINT32 Reserved : 22; // bit 10..31
+ } Bits;
+ UINT32 Uint32;
+} PCI_REG_PCIE_DEVICE_CAPABILITY3;
+
+typedef union {
+ struct {
+ UINT32 DmwrRequesterEnable : 1; // bit 0
+ UINT32 DmwrEgressBlocking : 1; // bit 1
+ UINT32 FourteenBitTagRequesterEnable : 1; // bit 2
+ UINT32 L0pEnable : 1; // bit 3
+ UINT32 TargetLinkWidth : 3; // bit 4..6
+ UINT32 Reserved : 25; // bit 7..31
+ } Bits;
+ UINT32 Uint32;
+} PCI_REG_PCIE_DEVICE_CONTROL3;
+
+typedef union {
+ struct {
+ UINT32 InitialLinkWidth : 3; // bit 0..2
+ UINT32 SegmentCaptured : 1; // bit 3
+ UINT32 RemoteL0pSupported : 1; // bit 4
+ UINT32 Reserved : 27; // bit 5..31
+ } Bits;
+ UINT32 Uint32;
+} PCI_REG_PCIE_DEVICE_STATUS3;
+
+#pragma pack()
+
+#endif
diff --git a/MdePkg/Include/IndustryStandard/ServiceProcessorManagementInterfaceTable.h b/MdePkg/Include/IndustryStandard/ServiceProcessorManagementInterfaceTable.h index 15f47f1..131cf40 100644..100755 --- a/MdePkg/Include/IndustryStandard/ServiceProcessorManagementInterfaceTable.h +++ b/MdePkg/Include/IndustryStandard/ServiceProcessorManagementInterfaceTable.h @@ -3,6 +3,8 @@ Intelligent Platform Management Interface Specification Second Generation.
Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2024 Advanced Micro Devices, Inc. All rights reserved.
+
SPDX-License-Identifier: BSD-2-Clause-Patent
@par Revision Reference:
@@ -95,4 +97,17 @@ typedef struct { #pragma pack()
+///
+/// SPMI Revision (defined in spec)
+///
+#define EFI_ACPI_SERVICE_PROCESSOR_MANAGEMENT_INTERFACE_5_TABLE_REVISION 0x05
+
+///
+/// SPMI Interface Type
+///
+#define EFI_ACPI_SPMI_INTERFACE_TYPE_KCS 0x01
+#define EFI_ACPI_SPMI_INTERFACE_TYPE_SMIC 0x02
+#define EFI_ACPI_SPMI_INTERFACE_TYPE_BT 0x03
+#define EFI_ACPI_SPMI_INTERFACE_TYPE_SSIF 0x04
+
#endif
diff --git a/MdePkg/Include/IndustryStandard/SmBios.h b/MdePkg/Include/IndustryStandard/SmBios.h index 020733b..8ba6129 100644 --- a/MdePkg/Include/IndustryStandard/SmBios.h +++ b/MdePkg/Include/IndustryStandard/SmBios.h @@ -887,7 +887,8 @@ typedef enum { ProcessorUpgradeSocketBGA2551 = 0x54,
ProcessorUpgradeSocketLGA1851 = 0x55,
ProcessorUpgradeSocketBGA2114 = 0x56,
- ProcessorUpgradeSocketBGA2833 = 0x57
+ ProcessorUpgradeSocketBGA2833 = 0x57,
+ ProcessorUpgradeInvalid = 0xFF
} PROCESSOR_UPGRADE;
///
@@ -1020,6 +1021,10 @@ typedef struct { // Add for smbios 3.6
//
UINT16 ThreadEnabled;
+ //
+ // Add for smbios 3.8
+ //
+ SMBIOS_TABLE_STRING SocketType;
} SMBIOS_TABLE_TYPE4;
///
@@ -1524,7 +1529,7 @@ typedef struct { UINT8 AsyncSurpriseRemoval : 1;
UINT8 FlexbusSlotCxl10Capable : 1;
UINT8 FlexbusSlotCxl20Capable : 1;
- UINT8 Reserved : 1; ///< Set to 0.
+ UINT8 FlexbusSlotCxl30Capable : 1; /// SMBIOS spec 3.7.0 updated CXL 3.0 support
} MISC_SLOT_CHARACTERISTICS2;
///
@@ -2027,6 +2032,13 @@ typedef struct { //
UINT32 ExtendedSpeed;
UINT32 ExtendedConfiguredMemorySpeed;
+ //
+ // Add for smbios 3.7.0
+ //
+ UINT16 Pmic0ManufacturerID;
+ UINT16 Pmic0RevisionNumber;
+ UINT16 RcdManufacturerID;
+ UINT16 RcdRevisionNumber;
} SMBIOS_TABLE_TYPE17;
///
diff --git a/MdePkg/Include/IndustryStandard/Tpm20.h b/MdePkg/Include/IndustryStandard/Tpm20.h index 4440f37..9303f16 100644 --- a/MdePkg/Include/IndustryStandard/Tpm20.h +++ b/MdePkg/Include/IndustryStandard/Tpm20.h @@ -203,15 +203,16 @@ typedef UINT16 TPM_ALG_ID; // Table 8 - TPM_ECC_CURVE Constants
typedef UINT16 TPM_ECC_CURVE;
-#define TPM_ECC_NONE (TPM_ECC_CURVE)(0x0000)
-#define TPM_ECC_NIST_P192 (TPM_ECC_CURVE)(0x0001)
-#define TPM_ECC_NIST_P224 (TPM_ECC_CURVE)(0x0002)
-#define TPM_ECC_NIST_P256 (TPM_ECC_CURVE)(0x0003)
-#define TPM_ECC_NIST_P384 (TPM_ECC_CURVE)(0x0004)
-#define TPM_ECC_NIST_P521 (TPM_ECC_CURVE)(0x0005)
-#define TPM_ECC_BN_P256 (TPM_ECC_CURVE)(0x0010)
-#define TPM_ECC_BN_P638 (TPM_ECC_CURVE)(0x0011)
-#define TPM_ECC_SM2_P256 (TPM_ECC_CURVE)(0x0020)
+#define TPM_ECC_NONE (TPM_ECC_CURVE)(0x0000)
+#define TPM_ECC_NIST_P192 (TPM_ECC_CURVE)(0x0001)
+#define TPM_ECC_NIST_P224 (TPM_ECC_CURVE)(0x0002)
+#define TPM_ECC_NIST_P256 (TPM_ECC_CURVE)(0x0003)
+#define TPM_ECC_NIST_P384 (TPM_ECC_CURVE)(0x0004)
+#define TPM_ECC_NIST_P521 (TPM_ECC_CURVE)(0x0005)
+#define TPM_ECC_BN_P256 (TPM_ECC_CURVE)(0x0010)
+#define TPM_ECC_BN_P638 (TPM_ECC_CURVE)(0x0011)
+#define TPM_ECC_SM2_P256 (TPM_ECC_CURVE)(0x0020)
+#define TPM_ECC_BP_P512_R1 (TPM_ECC_CURVE)(0x0032)
// Table 11 - TPM_CC Constants (Numeric Order)
typedef UINT32 TPM_CC;
diff --git a/MdePkg/Include/IndustryStandard/Tpm2Acpi.h b/MdePkg/Include/IndustryStandard/Tpm2Acpi.h index e7d14f9..882e21d 100644 --- a/MdePkg/Include/IndustryStandard/Tpm2Acpi.h +++ b/MdePkg/Include/IndustryStandard/Tpm2Acpi.h @@ -3,6 +3,7 @@ Copyright (c) 2013 - 2019, Intel Corporation. All rights reserved. <BR>
Copyright (c) 2021, Ampere Computing LLC. All rights reserved. <BR>
+Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. <BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -18,6 +19,9 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #define EFI_TPM2_ACPI_TABLE_REVISION_4 4
#define EFI_TPM2_ACPI_TABLE_REVISION EFI_TPM2_ACPI_TABLE_REVISION_4
+#define EFI_TPM2_ACPI_TABLE_START_METHOD_SPECIFIC_PARAMETERS_MAX_SIZE_REVISION_4 12
+#define EFI_TPM2_ACPI_TABLE_START_METHOD_SPECIFIC_PARAMETERS_MAX_SIZE EFI_TPM2_ACPI_TABLE_START_METHOD_SPECIFIC_PARAMETERS_MAX_SIZE_REVISION_4
+
typedef struct {
EFI_ACPI_DESCRIPTION_HEADER Header;
// Flags field is replaced in version 4 and above
diff --git a/MdePkg/Include/Library/ArmLib.h b/MdePkg/Include/Library/ArmLib.h index 6a1503a..087cddf 100644 --- a/MdePkg/Include/Library/ArmLib.h +++ b/MdePkg/Include/Library/ArmLib.h @@ -182,24 +182,6 @@ ArmIsMpCore ( VOID
EFIAPI
-ArmInvalidateDataCache (
- VOID
- );
-
-VOID
-EFIAPI
-ArmCleanInvalidateDataCache (
- VOID
- );
-
-VOID
-EFIAPI
-ArmCleanDataCache (
- VOID
- );
-
-VOID
-EFIAPI
ArmInvalidateInstructionCache (
VOID
);
diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/BaseLib.h index 95f8055..9658026 100644 --- a/MdePkg/Include/Library/BaseLib.h +++ b/MdePkg/Include/Library/BaseLib.h @@ -7,6 +7,7 @@ Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> Copyright (c) Microsoft Corporation.<BR>
Portions Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
Portions Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.<BR>
+Copyright (c) 2023 - 2024, Arm Limited. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -126,6 +127,92 @@ typedef struct { #define BASE_LIBRARY_JUMP_BUFFER_ALIGNMENT 8
+/**
+ Reads the current value of CNTPCT_EL0 register.
+
+ Reads and returns the current value of CNTPCT_EL0.
+ This function is only available on AARCH64.
+
+ @return The current value of CNTPCT_EL0
+**/
+UINT64
+EFIAPI
+ArmReadCntPctReg (
+ VOID
+ );
+
+//
+// Bit shifts for the ID_AA64ISAR0_EL1 register.
+//
+#define ARM_ID_AA64ISAR0_EL1_AES_SHIFT (4U)
+#define ARM_ID_AA64ISAR0_EL1_SHA1_SHIFT (8U)
+#define ARM_ID_AA64ISAR0_EL1_SHA2_SHIFT (12U)
+#define ARM_ID_AA64ISAR0_EL1_CRC32_SHIFT (16U)
+#define ARM_ID_AA64ISAR0_EL1_ATOMIC_SHIFT (20U)
+#define ARM_ID_AA64ISAR0_EL1_RDM_SHIFT (28U)
+#define ARM_ID_AA64ISAR0_EL1_SHA3_SHIFT (32U)
+#define ARM_ID_AA64ISAR0_EL1_SM3_SHIFT (36U)
+#define ARM_ID_AA64ISAR0_EL1_SM4_SHIFT (40U)
+#define ARM_ID_AA64ISAR0_EL1_DP_SHIFT (44U)
+#define ARM_ID_AA64ISAR0_EL1_FHM_SHIFT (48U)
+#define ARM_ID_AA64ISAR0_EL1_TS_SHIFT (52U)
+#define ARM_ID_AA64ISAR0_EL1_TLB_SHIFT (56U)
+#define ARM_ID_AA64ISAR0_EL1_RNDR_SHIFT (60U)
+
+//
+// Bit masks for the ID_AA64ISAR0_EL1 fields.
+//
+#define ARM_ID_AA64ISAR0_EL1_AES_MASK (0xFU)
+#define ARM_ID_AA64ISAR0_EL1_SHA1_MASK (0xFU)
+#define ARM_ID_AA64ISAR0_EL1_SHA2_MASK (0xFU)
+#define ARM_ID_AA64ISAR0_EL1_CRC32_MASK (0xFU)
+#define ARM_ID_AA64ISAR0_EL1_ATOMIC_MASK (0xFU)
+#define ARM_ID_AA64ISAR0_EL1_RDM_MASK (0xFU)
+#define ARM_ID_AA64ISAR0_EL1_SHA3_MASK (0xFU)
+#define ARM_ID_AA64ISAR0_EL1_SM3_MASK (0xFU)
+#define ARM_ID_AA64ISAR0_EL1_SM4_MASK (0xFU)
+#define ARM_ID_AA64ISAR0_EL1_DP_MASK (0xFU)
+#define ARM_ID_AA64ISAR0_EL1_FHM_MASK (0xFU)
+#define ARM_ID_AA64ISAR0_EL1_TS_MASK (0xFU)
+#define ARM_ID_AA64ISAR0_EL1_TLB_MASK (0xFU)
+#define ARM_ID_AA64ISAR0_EL1_RNDR_MASK (0xFU)
+
+//
+// Bit masks for the ID_AA64ISAR0_EL1 field values.
+//
+#define ARM_ID_AA64ISAR0_EL1_AES_FEAT_AES_MASK (0x1U)
+#define ARM_ID_AA64ISAR0_EL1_AES_FEAT_PMULL_MASK (0x2U)
+#define ARM_ID_AA64ISAR0_EL1_SHA1_FEAT_SHA1_MASK (0x1U)
+#define ARM_ID_AA64ISAR0_EL1_SHA2_FEAT_SHA256_MASK (0x1U)
+#define ARM_ID_AA64ISAR0_EL1_SHA2_FEAT_SHA512_MASK (0x2U)
+#define ARM_ID_AA64ISAR0_EL1_CRC32_HAVE_CRC32_MASK (0x1U)
+#define ARM_ID_AA64ISAR0_EL1_ATOMIC_FEAT_LSE_MASK (0x2U)
+#define ARM_ID_AA64ISAR0_EL1_RDM_FEAT_RDM_MASK (0x1U)
+#define ARM_ID_AA64ISAR0_EL1_SHA3_FEAT_SHA3_MASK (0x1U)
+#define ARM_ID_AA64ISAR0_EL1_SM3_FEAT_SM3_MASK (0x1U)
+#define ARM_ID_AA64ISAR0_EL1_SM4_FEAT_SM4_MASK (0x1U)
+#define ARM_ID_AA64ISAR0_EL1_DP_FEAT_DOTPROD_MASK (0x1U)
+#define ARM_ID_AA64ISAR0_EL1_FHM_FEAT_FHM_MASK (0x1U)
+#define ARM_ID_AA64ISAR0_EL1_TS_FEAT_FLAGM_MASK (0x1U)
+#define ARM_ID_AA64ISAR0_EL1_TS_FEAT_FLAGM2_MASK (0x2U)
+#define ARM_ID_AA64ISAR0_EL1_TLB_FEAT_TLBIOS_MASK (0x1U)
+#define ARM_ID_AA64ISAR0_EL1_TLB_FEAT_TLBIRANGE_MASK (0x2U)
+#define ARM_ID_AA64ISAR0_EL1_RNDR_FEAT_RNG_MASK (0x1U)
+
+/**
+ Reads the current value of ID_AA64ISAR0_EL1 register.
+
+ Reads and returns the current value of ID_AA64ISAR0_EL1.
+ This function is only available on AARCH64.
+
+ @return The current value of ID_AA64ISAR0_EL1
+**/
+UINT64
+EFIAPI
+ArmReadIdAA64Isar0Reg (
+ VOID
+ );
+
#endif // defined (MDE_CPU_AARCH64)
#if defined (MDE_CPU_RISCV64)
@@ -4900,6 +4987,23 @@ CalculateCrc32c ( IN UINT32 InitialValue
);
+/**
+ Calculates the CRC16-CCITT-FALSE checksum of the given buffer.
+
+ @param[in] Buffer Pointer to the buffer.
+ @param[in] Length Length of the buffer, in bytes.
+ @param[in] InitialValue Initial value of the CRC.
+
+ @return The CRC16-CCITT-FALSE checksum.
+**/
+UINT16
+EFIAPI
+CalculateCrc16CcittF (
+ IN CONST VOID *Buffer,
+ IN UINTN Length,
+ IN UINT16 InitialValue
+ );
+
//
// Base Library CPU Functions
//
@@ -5155,8 +5259,6 @@ SpeculationBarrier ( VOID
);
-#if defined (MDE_CPU_X64) || defined (MDE_CPU_IA32)
-
/**
The TDCALL instruction causes a VM exit to the Intel TDX module. It is
used to call guest-side Intel TDX functions, either local or a TD exit
@@ -5219,8 +5321,6 @@ TdIsEnabled ( VOID
);
-#endif
-
#if defined (MDE_CPU_X64)
//
// The page size for the PVALIDATE instruction
diff --git a/MdePkg/Include/Library/DebugLib.h b/MdePkg/Include/Library/DebugLib.h index 0db3b78..033c4e1 100644 --- a/MdePkg/Include/Library/DebugLib.h +++ b/MdePkg/Include/Library/DebugLib.h @@ -342,13 +342,13 @@ UnitTestDebugAssert ( #if defined (_ASSERT)
#undef _ASSERT
#endif
- #if defined (__clang__) && defined (__FILE_NAME__)
+ #if defined (__FILE_NAME__)
#define _ASSERT(Expression) UnitTestDebugAssert (__FILE_NAME__, DEBUG_LINE_NUMBER, DEBUG_EXPRESSION_STRING (Expression))
#else
#define _ASSERT(Expression) UnitTestDebugAssert (__FILE__, DEBUG_LINE_NUMBER, DEBUG_EXPRESSION_STRING (Expression))
#endif
#else
- #if defined (__clang__) && defined (__FILE_NAME__)
+ #if defined (__FILE_NAME__)
#define _ASSERT(Expression) DebugAssert (__FILE_NAME__, DEBUG_LINE_NUMBER, DEBUG_EXPRESSION_STRING (Expression))
#else
#define _ASSERT(Expression) DebugAssert (__FILE__, DEBUG_LINE_NUMBER, DEBUG_EXPRESSION_STRING (Expression))
@@ -534,7 +534,10 @@ UnitTestDebugAssert ( are not included in a module.
**/
-#define DEBUG_CODE_BEGIN() do { if (DebugCodeEnabled ()) { UINT8 __DebugCodeLocal
+#define DEBUG_CODE_BEGIN() \
+ do { \
+ if (DebugCodeEnabled ()) { \
+ do { } while (FALSE)
/**
The macro that marks the end of debug source code.
@@ -545,7 +548,9 @@ UnitTestDebugAssert ( are not included in a module.
**/
-#define DEBUG_CODE_END() __DebugCodeLocal = 0; __DebugCodeLocal++; } } while (FALSE)
+#define DEBUG_CODE_END() \
+ } \
+ } while (FALSE)
/**
The macro that declares a section of debug source code.
@@ -588,8 +593,12 @@ UnitTestDebugAssert ( If MDEPKG_NDEBUG is defined or the DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED bit
of PcdDebugProperyMask is clear, then this macro computes the offset, in bytes,
of the field specified by Field from the beginning of the data structure specified
- by TYPE. This offset is subtracted from Record, and is used to return a pointer
- to a data structure of the type specified by TYPE.
+ by TYPE. This offset is subtracted from Record, and is used to compute a pointer
+ to a data structure of the type specified by TYPE. The Signature field of the
+ data structure specified by TYPE is compared to TestSignature. If the signatures
+ match, then a pointer to the pointer to a data structure of the type specified by
+ TYPE is returned. If the signatures do not match, then NULL is returned to
+ signify that the passed in data structure is invalid.
If MDEPKG_NDEBUG is not defined and the DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED bit
of PcdDebugProperyMask is set, then this macro computes the offset, in bytes,
@@ -623,9 +632,13 @@ UnitTestDebugAssert ( #define CR(Record, TYPE, Field, TestSignature) \
(DebugAssertEnabled () && (BASE_CR (Record, TYPE, Field)->Signature != TestSignature)) ? \
(TYPE *) (_ASSERT (CR has Bad Signature), Record) : \
+ (BASE_CR (Record, TYPE, Field)->Signature != TestSignature) ? \
+ NULL : \
BASE_CR (Record, TYPE, Field)
#else
#define CR(Record, TYPE, Field, TestSignature) \
+ (BASE_CR (Record, TYPE, Field)->Signature != TestSignature) ? \
+ NULL : \
BASE_CR (Record, TYPE, Field)
#endif
diff --git a/MdePkg/Include/Library/FdtLib.h b/MdePkg/Include/Library/FdtLib.h index 65d7460..a7d26f7 100644 --- a/MdePkg/Include/Library/FdtLib.h +++ b/MdePkg/Include/Library/FdtLib.h @@ -19,6 +19,115 @@ #ifndef FDT_LIB_H_
#define FDT_LIB_H_
+/* Error codes: informative error codes */
+#define FDT_ERR_NOTFOUND 1
+/* FDT_ERR_NOTFOUND: The requested node or property does not exist */
+#define FDT_ERR_EXISTS 2
+
+/* FDT_ERR_EXISTS: Attempted to create a node or property which
+ * already exists */
+#define FDT_ERR_NOSPACE 3
+
+/* FDT_ERR_NOSPACE: Operation needed to expand the device
+ * tree, but its buffer did not have sufficient space to
+ * contain the expanded tree. Use fdt_open_into() to move the
+ * device tree to a buffer with more space. */
+
+/* Error codes: codes for bad parameters */
+#define FDT_ERR_BADOFFSET 4
+
+/* FDT_ERR_BADOFFSET: Function was passed a structure block
+ * offset which is out-of-bounds, or which points to an
+ * unsuitable part of the structure for the operation. */
+#define FDT_ERR_BADPATH 5
+
+/* FDT_ERR_BADPATH: Function was passed a badly formatted path
+ * (e.g. missing a leading / for a function which requires an
+ * absolute path) */
+#define FDT_ERR_BADPHANDLE 6
+
+/* FDT_ERR_BADPHANDLE: Function was passed an invalid phandle.
+ * This can be caused either by an invalid phandle property
+ * length, or the phandle value was either 0 or -1, which are
+ * not permitted. */
+#define FDT_ERR_BADSTATE 7
+
+/* FDT_ERR_BADSTATE: Function was passed an incomplete device
+ * tree created by the sequential-write functions, which is
+ * not sufficiently complete for the requested operation. */
+
+/* Error codes: codes for bad device tree blobs */
+#define FDT_ERR_TRUNCATED 8
+
+/* FDT_ERR_TRUNCATED: FDT or a sub-block is improperly
+ * terminated (overflows, goes outside allowed bounds, or
+ * isn't properly terminated). */
+#define FDT_ERR_BADMAGIC 9
+
+/* FDT_ERR_BADMAGIC: Given "device tree" appears not to be a
+ * device tree at all - it is missing the flattened device
+ * tree magic number. */
+#define FDT_ERR_BADVERSION 10
+
+/* FDT_ERR_BADVERSION: Given device tree has a version which
+ * can't be handled by the requested operation. For
+ * read-write functions, this may mean that fdt_open_into() is
+ * required to convert the tree to the expected version. */
+#define FDT_ERR_BADSTRUCTURE 11
+
+/* FDT_ERR_BADSTRUCTURE: Given device tree has a corrupt
+ * structure block or other serious error (e.g. misnested
+ * nodes, or subnodes preceding properties). */
+#define FDT_ERR_BADLAYOUT 12
+
+/* FDT_ERR_BADLAYOUT: For read-write functions, the given
+ * device tree has it's sub-blocks in an order that the
+ * function can't handle (memory reserve map, then structure,
+ * then strings). Use fdt_open_into() to reorganize the tree
+ * into a form suitable for the read-write operations. */
+
+/* "Can't happen" error indicating a bug in libfdt */
+#define FDT_ERR_INTERNAL 13
+
+/* FDT_ERR_INTERNAL: libfdt has failed an internal assertion.
+ * Should never be returned, if it is, it indicates a bug in
+ * libfdt itself. */
+
+/* Errors in device tree content */
+#define FDT_ERR_BADNCELLS 14
+
+/* FDT_ERR_BADNCELLS: Device tree has a #address-cells, #size-cells
+ * or similar property with a bad format or value */
+
+#define FDT_ERR_BADVALUE 15
+
+/* FDT_ERR_BADVALUE: Device tree has a property with an unexpected
+ * value. For example: a property expected to contain a string list
+ * is not NUL-terminated within the length of its value. */
+
+#define FDT_ERR_BADOVERLAY 16
+
+/* FDT_ERR_BADOVERLAY: The device tree overlay, while
+ * correctly structured, cannot be applied due to some
+ * unexpected or missing value, property or node. */
+
+#define FDT_ERR_NOPHANDLES 17
+
+/* FDT_ERR_NOPHANDLES: The device tree doesn't have any
+ * phandle available anymore without causing an overflow */
+
+#define FDT_ERR_BADFLAGS 18
+
+/* FDT_ERR_BADFLAGS: The function was passed a flags field that
+ * contains invalid flags or an invalid combination of flags. */
+
+#define FDT_ERR_ALIGNMENT 19
+
+/* FDT_ERR_ALIGNMENT: The device tree base address is not 8-byte
+ * aligned. */
+
+#define FDT_ERR_MAX 19
+
/**
Flattened Device Tree definition
@@ -63,6 +172,22 @@ typedef struct { CHAR8 Data[];
} FDT_PROPERTY;
+#ifndef FDT_TAGSIZE
+#define FDT_TAGSIZE sizeof(UINT32)
+#endif
+#ifndef FDT_MAX_NCELLS
+#define FDT_MAX_NCELLS 4
+#endif
+
+#define FdtGetHeader(Fdt, Field) \
+ (Fdt32ToCpu (((const FDT_HEADER *)(Fdt))->Field))
+#define FdtTotalSize(Fdt) (FdtGetHeader ((Fdt), TotalSize))
+
+#define FdtForEachSubnode(Node, Fdt, Parent) \
+ for (Node = FdtFirstSubnode (Fdt, Parent); \
+ Node >= 0; \
+ Node = FdtNextSubnode (Fdt, Node))
+
/**
Convert UINT16 data of the FDT blob to little-endian
@@ -162,6 +287,37 @@ FdtCheckHeader ( );
/**
+ Unpack FDT blob into new buffer
+
+ @param[in] Fdt The pointer to FDT blob.
+ @param[out] Buffer Pointer to destination buffer.
+ @param[in] BufferSize The size of destination buffer.
+
+ @return Zero for successfully, otherwise failed.
+
+ **/
+INT32
+EFIAPI
+FdtOpenInto (
+ IN CONST VOID *Fdt,
+ OUT VOID *Buffer,
+ IN INT32 BufferSize
+ );
+
+/**
+ Pack FDT blob in place.
+
+ @param[in][out] Fdt The pointer to FDT blob.
+
+ @return Zero.
+**/
+INT32
+EFIAPI
+FdtPack (
+ IN OUT VOID *Fdt
+ );
+
+/**
Create a empty Flattened Device Tree.
@param[in] Buffer The pointer to allocate a pool for FDT blob.
@@ -178,6 +334,23 @@ FdtCreateEmptyTree ( );
/**
+ Returns a pointer to the node at a given offset.
+
+ @param[in] Fdt The pointer to FDT blob.
+ @param[in] Offset The offset to node.
+ @param[in] Length Maximum length of node.
+
+ @return pointer to node.
+**/
+CONST VOID *
+EFIAPI
+FdtOffsetPointer (
+ IN CONST VOID *Fdt,
+ IN INT32 Offset,
+ IN UINT32 Length
+ );
+
+/**
Returns a offset of next node from the given node.
@param[in] Fdt The pointer to FDT blob.
@@ -248,6 +421,55 @@ FdtSubnodeOffsetNameLen ( );
/**
+ Returns the number of memory reserve map entries.
+
+ @param[in] Fdt The pointer to FDT blob.
+
+ @return The number of entries in the reserve map.
+
+**/
+INTN
+EFIAPI
+FdtGetNumberOfReserveMapEntries (
+ IN CONST VOID *Fdt
+ );
+
+/**
+ Returns a memory reserve map entry.
+
+ @param[in] *Fdt The pointer to FDT blob.
+ @param[in] Index Index of reserve map entry.
+ @param[out] Addr Pointer to 64-bit variable to hold the start address
+ @param[out] *Size Pointer to 64-bit variable to hold size of reservation
+
+ @return 0 on success, or negative error code.
+
+**/
+INTN
+EFIAPI
+FdtGetReserveMapEntry (
+ IN CONST VOID *Fdt,
+ IN INTN Index,
+ OUT UINT64 *Addr,
+ OUT UINT64 *Size
+ );
+
+/**
+ Find the parent of a given node.
+
+ @param[in] Fdt The pointer to FDT blob.
+ @param[in] NodeOffset The offset to the node to find the parent for.
+
+ @return Structure block offset, or negative return value.
+**/
+INT32
+EFIAPI
+FdtParentOffset (
+ IN CONST VOID *Fdt,
+ IN INT32 NodeOffset
+ );
+
+/**
Returns a offset of first node which includes the given property name and value.
@param[in] Fdt The pointer to FDT blob.
@@ -261,7 +483,7 @@ FdtSubnodeOffsetNameLen ( **/
INT32
EFIAPI
-FdtNodeOffsetByPropValue (
+FdtNodeOffsetByPropertyValue (
IN CONST VOID *Fdt,
IN INT32 StartOffset,
IN CONST CHAR8 *PropertyName,
@@ -270,6 +492,38 @@ FdtNodeOffsetByPropValue ( );
/**
+ Returns a offset of first node which includes the given property name and value.
+
+ @param[in] Fdt The pointer to FDT blob.
+ @param[in] Phandle Phandle value to search for.
+
+ @return The offset to node with matching Phandle value.
+**/
+INT32
+EFIAPI
+FdtNodeOffsetByPhandle (
+ IN CONST VOID *Fdt,
+ IN UINT32 Phandle
+ );
+
+/**
+ Look for a string in a stringlist
+
+ @param[in] StringList Pointer to stringlist to search.
+ @param[in] ListLength Length of StringList.
+ @param[in] String Pointer to string to search for.
+
+ @return 1 if found.
+**/
+INT32
+EFIAPI
+FdtStringListContains (
+ IN CONST CHAR8 *StringList,
+ IN INT32 ListLength,
+ IN CONST CHAR8 *String
+ );
+
+/**
Returns a property with the given name from the given node.
@param[in] Fdt The pointer to FDT blob.
@@ -291,6 +545,25 @@ FdtGetProperty ( );
/**
+ Returns a pointer to a node mapped to an alias matching a substring.
+
+ @param[in] Fdt The pointer to FDT blob.
+ @param[in] Name The alias name string.
+ @param[in] Length The length to the size of the property found.
+
+ @return A pointer to the expansion of the alias matching the substring,
+ or NULL if alias not found.
+
+**/
+CONST CHAR8 *
+EFIAPI
+FdtGetAliasNameLen (
+ IN CONST VOID *Fdt,
+ IN CONST CHAR8 *Name,
+ IN INT32 Length
+ );
+
+/**
Returns a offset of first property in the given node.
@param[in] Fdt The pointer to FDT blob.
@@ -390,7 +663,49 @@ FdtAddSubnode ( **/
INT32
EFIAPI
-FdtSetProp (
+FdtSetProperty (
+ IN VOID *Fdt,
+ IN INT32 NodeOffset,
+ IN CONST CHAR8 *Name,
+ IN CONST VOID *Value,
+ IN UINT32 Length
+ );
+
+/**
+ Set a property to a 64-bit integer.
+
+ @param[in] Fdt The pointer to FDT blob.
+ @param[in] NodeOffset The offset to the node offset which want to add in.
+ @param[in] Name The name to name the property.
+ @param[in] Value The value (big-endian) to the property value.
+
+ @return Zero for successfully, otherwise failed.
+
+ **/
+INT32
+EFIAPI
+FdtSetPropU64 (
+ IN VOID *Fdt,
+ IN INT32 NodeOffset,
+ IN CONST CHAR8 *Name,
+ IN UINT64 Value
+ );
+
+/**
+ Append or create a property in the given node.
+
+ @param[in] Fdt The pointer to FDT blob.
+ @param[in] NodeOffset The offset to the node offset which want to add in.
+ @param[in] Name The name to name the property.
+ @param[in] Value The value (big-endian) to the property value.
+ @param[in] Length The length to the size of the property.
+
+ @return Zero for successfully, otherwise failed.
+
+ **/
+INT32
+EFIAPI
+FdtAppendProp (
IN VOID *Fdt,
IN INT32 NodeOffset,
IN CONST CHAR8 *Name,
@@ -399,6 +714,58 @@ FdtSetProp ( );
/**
+ Delete a property.
+
+ This function will delete data from the blob, and will therefore
+ change the offsets of some existing nodes.
+
+ @param[in][out] Fdt Pointer to the device tree blob.
+ @param[in] NodeOffset Offset of the node whose property to nop.
+ @param[in] Name Name of the property to nop.
+
+ @return Zero for successfully, otherwise failed.
+
+**/
+INT32
+FdtDelProp (
+ IN OUT VOID *Fdt,
+ IN INT32 NodeOffset,
+ IN CONST CHAR8 *Name
+ );
+
+/**
+ Finds a tree node by substring
+
+ @param[in] Fdt The pointer to FDT blob.
+ @param[in] Path Full path of the node to locate.
+ @param[in] NameLength The length of the name to check only.
+
+ @return structure block offset of the node with the requested path (>=0), on success
+**/
+INT32
+EFIAPI
+FdtPathOffsetNameLen (
+ IN CONST VOID *Fdt,
+ IN CONST CHAR8 *Path,
+ IN INT32 NameLength
+ );
+
+/**
+ Finds a tree node by its full path.
+
+ @param[in] Fdt The pointer to FDT blob.
+ @param[in] Path Full path of the node to locate.
+
+ @return structure block offset of the node with the requested path (>=0), on success
+**/
+INT32
+EFIAPI
+FdtPathOffset (
+ IN CONST VOID *Fdt,
+ IN CONST CHAR8 *Path
+ );
+
+/**
Returns the name of a given node.
@param[in] Fdt The pointer to FDT blob.
@@ -432,4 +799,59 @@ FdtNodeDepth ( IN INT32 NodeOffset
);
+/**
+ Find nodes with a given 'compatible' value.
+
+ @param[in] Fdt The pointer to FDT blob.
+ @param[in] StartOffset Only find nodes after this offset.
+ @param[in] Compatible The string to match against.
+
+ @retval The offset of the first node after StartOffset.
+**/
+INT32
+EFIAPI
+FdtNodeOffsetByCompatible (
+ IN CONST VOID *Fdt,
+ IN INT32 StartOffset,
+ IN CONST CHAR8 *Compatible
+ );
+
+/**
+ Retrieve address size for a bus represented in the tree
+
+ @param[in] Fdt The pointer to FDT blob.
+ @param[in] NodeOffset Offset of node to check.
+
+ @return Number of cells in the bus address, or negative error.
+**/
+INT32
+EFIAPI
+FdtAddressCells (
+ IN CONST VOID *Fdt,
+ IN INT32 NodeOffset
+ );
+
+/**
+ Retrieve address range size for a bus represented in the tree
+
+ @param[in] Fdt The pointer to FDT blob.
+ @param[in] NodeOffset Offset of node to check.
+
+ @return Number of cells in the bus size, or negative error.
+**/
+INT32
+EFIAPI
+FdtSizeCells (
+ IN CONST VOID *Fdt,
+ IN INT32 NodeOffset
+ );
+
+/* Debug functions. */
+CONST
+CHAR8
+*
+FdtStrerror (
+ IN INT32 ErrVal
+ );
+
#endif /* FDT_LIB_H_ */
diff --git a/MdePkg/Include/Library/PerformanceLib.h b/MdePkg/Include/Library/PerformanceLib.h index d0f2dfb..40e99d0 100644 --- a/MdePkg/Include/Library/PerformanceLib.h +++ b/MdePkg/Include/Library/PerformanceLib.h @@ -734,7 +734,10 @@ LogPerformanceMeasurement ( Otherwise, the source lines between PERF_CODE_BEGIN() and PERF_CODE_END() are not included in a module.
**/
-#define PERF_CODE_BEGIN() do { if (PerformanceMeasurementEnabled ()) { UINT8 __PerformanceCodeLocal
+#define PERF_CODE_BEGIN() \
+ do { \
+ if (PerformanceMeasurementEnabled ()) { \
+ do { } while (FALSE)
/**
Macro that marks the end of performance measurement source code.
@@ -744,7 +747,9 @@ LogPerformanceMeasurement ( Otherwise, the source lines between PERF_CODE_BEGIN() and PERF_CODE_END() are not included in a module.
**/
-#define PERF_CODE_END() __PerformanceCodeLocal = 0; __PerformanceCodeLocal++; } } while (FALSE)
+#define PERF_CODE_END() \
+ } \
+ } while (FALSE)
/**
Macro that declares a section of performance measurement source code.
diff --git a/MdePkg/Include/Library/StackCheckFailureHookLib.h b/MdePkg/Include/Library/StackCheckFailureHookLib.h new file mode 100644 index 0000000..f0657dd --- /dev/null +++ b/MdePkg/Include/Library/StackCheckFailureHookLib.h @@ -0,0 +1,26 @@ +/** @file
+ Library provides a hook called when a stack cookie check fails.
+
+ Copyright (c) Microsoft Corporation.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef STACK_COOKIE_FAILURE_HOOK_LIB_H_
+#define STACK_COOKIE_FAILURE_HOOK_LIB_H_
+
+#include <Uefi.h>
+
+/**
+ This function gets called when a compiler generated stack cookie fails. This allows a platform to hook this
+ call and perform any required actions/telemetry at that time.
+
+ @param FailureAddress The address of the function that failed the stack cookie check.
+
+**/
+VOID
+EFIAPI
+StackCheckFailureHook (
+ VOID *FailureAddress
+ );
+
+#endif
diff --git a/MdePkg/Include/Protocol/Http.h b/MdePkg/Include/Protocol/Http.h index 28e6221..7d9481a 100644 --- a/MdePkg/Include/Protocol/Http.h +++ b/MdePkg/Include/Protocol/Http.h @@ -98,7 +98,8 @@ typedef enum { HTTP_STATUS_503_SERVICE_UNAVAILABLE,
HTTP_STATUS_504_GATEWAY_TIME_OUT,
HTTP_STATUS_505_HTTP_VERSION_NOT_SUPPORTED,
- HTTP_STATUS_308_PERMANENT_REDIRECT
+ HTTP_STATUS_308_PERMANENT_REDIRECT,
+ HTTP_STATUS_429_TOO_MANY_REQUESTS
} EFI_HTTP_STATUS_CODE;
///
diff --git a/MdePkg/Include/Protocol/Smbios.h b/MdePkg/Include/Protocol/Smbios.h index f9346aa..e6977b4 100644 --- a/MdePkg/Include/Protocol/Smbios.h +++ b/MdePkg/Include/Protocol/Smbios.h @@ -69,6 +69,10 @@ #define EFI_SMBIOS_TYPE_ADDITIONAL_INFORMATION SMBIOS_TYPE_ADDITIONAL_INFORMATION
#define EFI_SMBIOS_TYPE_ONBOARD_DEVICES_EXTENDED_INFORMATION SMBIOS_TYPE_ONBOARD_DEVICES_EXTENDED_INFORMATION
#define EFI_SMBIOS_TYPE_MANAGEMENT_CONTROLLER_HOST_INTERFACE SMBIOS_TYPE_MANAGEMENT_CONTROLLER_HOST_INTERFACE
+#define EFI_SMBIOS_TYPE_TPM_DEVICE SMBIOS_TYPE_TPM_DEVICE
+#define EFI_SMBIOS_TYPE_PROCESSOR_ADDITIONAL_INFORMATION SMBIOS_TYPE_PROCESSOR_ADDITIONAL_INFORMATION
+#define EFI_SMBIOS_TYPE_FIRMWARE_INVENTORY_INFORMATION SMBIOS_TYPE_FIRMWARE_INVENTORY_INFORMATION
+#define EFI_SMBIOS_TYPE_STRING_PROPERTY_INFORMATION SMBIOS_TYPE_STRING_PROPERTY_INFORMATION
#define EFI_SMBIOS_TYPE_INACTIVE SMBIOS_TYPE_INACTIVE
#define EFI_SMBIOS_TYPE_END_OF_TABLE SMBIOS_TYPE_END_OF_TABLE
#define EFI_SMBIOS_OEM_BEGIN SMBIOS_OEM_BEGIN
diff --git a/MdePkg/Include/Register/Intel/StmApi.h b/MdePkg/Include/Register/Intel/StmApi.h index 9d42bcd..6c1cdf9 100644 --- a/MdePkg/Include/Register/Intel/StmApi.h +++ b/MdePkg/Include/Register/Intel/StmApi.h @@ -18,6 +18,8 @@ #pragma pack (1)
+#define STM_SMM_REV_ID 0x80010100
+
/**
STM Header Structures
**/
diff --git a/MdePkg/Include/Register/LoongArch64/Csr.h b/MdePkg/Include/Register/LoongArch64/Csr.h index aa22a26..fe2ebd9 100644 --- a/MdePkg/Include/Register/LoongArch64/Csr.h +++ b/MdePkg/Include/Register/LoongArch64/Csr.h @@ -112,7 +112,7 @@ //
// Config CSR registers
//
-#define LOONGARCH_CSR_CPUNUM 0x20 // CPU core number
+#define LOONGARCH_CSR_CPUID 0x20 // CPU core ID
#define LOONGARCH_CSR_PRCFG1 0x21 // Config1
#define LOONGARCH_CSR_PRCFG2 0x22 // Config2
#define LOONGARCH_CSR_PRCFG3 0x23 // Config3
diff --git a/MdePkg/Include/Register/RiscV64/RiscVEncoding.h b/MdePkg/Include/Register/RiscV64/RiscVEncoding.h index 8ccdea2..ea148f7 100644 --- a/MdePkg/Include/Register/RiscV64/RiscVEncoding.h +++ b/MdePkg/Include/Register/RiscV64/RiscVEncoding.h @@ -20,6 +20,7 @@ #define MSTATUS_SPP (1UL << MSTATUS_SPP_SHIFT)
#define MSTATUS_MPP_SHIFT 11
#define MSTATUS_MPP (3UL << MSTATUS_MPP_SHIFT)
+#define MSTATUS_FS 0x00006000UL
#define SSTATUS_SIE MSTATUS_SIE
#define SSTATUS_SPIE_SHIFT MSTATUS_SPIE_SHIFT
@@ -76,6 +77,9 @@ #define CSR_CYCLE 0xc00
#define CSR_TIME 0xc01
+/* Floating-Point */
+#define CSR_FCSR 0x003
+
/* Supervisor Trap Setup */
#define CSR_SSTATUS 0x100
#define CSR_SEDELEG 0x102
@@ -120,4 +124,14 @@ #define CAUSE_VIRTUAL_INST_FAULT 0x16
#define CAUSE_STORE_GUEST_PAGE_FAULT 0x17
+/* Sstc extension */
+#define CSR_SEED 0x15
+
+#define SEED_OPST_MASK 0xc0000000
+#define SEED_OPST_BIST 0x00000000
+#define SEED_OPST_WAIT 0x40000000
+#define SEED_OPST_ES16 0x80000000
+#define SEED_OPST_DEAD 0xc0000000
+#define SEED_ENTROPY_MASK 0xffff
+
#endif
diff --git a/MdePkg/Include/Uefi/UefiMultiPhase.h b/MdePkg/Include/Uefi/UefiMultiPhase.h index 7884913..1f1f3f4 100644 --- a/MdePkg/Include/Uefi/UefiMultiPhase.h +++ b/MdePkg/Include/Uefi/UefiMultiPhase.h @@ -108,7 +108,22 @@ typedef enum { /// by a corresponding call to the underlying isolation architecture.
///
EfiUnacceptedMemoryType,
- EfiMaxMemoryType
+ EfiMaxMemoryType,
+ //
+ // +---------------------------------------------------+
+ // | 0..(EfiMaxMemoryType - 1) - Normal memory type |
+ // +---------------------------------------------------+
+ // | EfiMaxMemoryType..0x6FFFFFFF - Invalid |
+ // +---------------------------------------------------+
+ // | 0x70000000..0x7FFFFFFF - OEM reserved |
+ // +---------------------------------------------------+
+ // | 0x80000000..0xFFFFFFFF - OS reserved |
+ // +---------------------------------------------------+
+ //
+ MEMORY_TYPE_OEM_RESERVED_MIN = 0x70000000,
+ MEMORY_TYPE_OEM_RESERVED_MAX = 0x7FFFFFFF,
+ MEMORY_TYPE_OS_RESERVED_MIN = 0x80000000,
+ MEMORY_TYPE_OS_RESERVED_MAX = 0xFFFFFFFF
} EFI_MEMORY_TYPE;
///
|