diff options
Diffstat (limited to 'MdePkg')
56 files changed, 1431 insertions, 275 deletions
diff --git a/MdePkg/Include/Base.h b/MdePkg/Include/Base.h index 7caebbe..363e0fe 100644 --- a/MdePkg/Include/Base.h +++ b/MdePkg/Include/Base.h @@ -1058,7 +1058,7 @@ typedef UINTN RETURN_STATUS; @retval FALSE The high bit of StatusCode is clear.
**/
-#define RETURN_ERROR(StatusCode) (((INTN)(RETURN_STATUS)(StatusCode)) < 0)
+#define RETURN_ERROR(StatusCode) (((RETURN_STATUS)(StatusCode)) >= MAX_BIT)
///
/// The operation completed successfully.
diff --git a/MdePkg/Include/Guid/ConformanceProfiles.h b/MdePkg/Include/Guid/ConformanceProfiles.h new file mode 100644 index 0000000..bf89ab6 --- /dev/null +++ b/MdePkg/Include/Guid/ConformanceProfiles.h @@ -0,0 +1,67 @@ +/** @file
+ GUIDs used for UEFI Conformance Profiles Table in the UEFI 2.10 specification.
+
+ Copyright (c) 2024, Arm Limited. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef CONFORMANCE_PROFILES_TABLE_GUID_H_
+#define CONFORMANCE_PROFILES_TABLE_GUID_H_
+
+//
+// This table allows the platform to advertise its UEFI specification conformance
+// in the form of pre-defined profiles. Each profile is identified by a GUID, with
+// known profiles listed in the section below.
+// The absence of this table shall indicate that the platform implementation is
+// conformant with the UEFI specification requirements, as defined in Section 2.6.
+// This is equivalent to publishing this configuration table with the
+// EFI_CONFORMANCE_PROFILES_UEFI_SPEC_GUID conformance profile.
+//
+#define EFI_CONFORMANCE_PROFILES_TABLE_GUID \
+ { \
+ 0x36122546, 0xf7e7, 0x4c8f, { 0xbd, 0x9b, 0xeb, 0x85, 0x25, 0xb5, 0x0c, 0x0b } \
+ }
+
+#pragma pack(1)
+
+typedef struct {
+ ///
+ /// Version of the table must be 0x1
+ ///
+ UINT16 Version;
+ ///
+ /// The number of profiles GUIDs present in ConformanceProfiles
+ ///
+ UINT16 NumberOfProfiles;
+ ///
+ /// An array of conformance profile GUIDs that are supported by this system.
+ /// EFI_GUID ConformanceProfiles[];
+ ///
+} EFI_CONFORMANCE_PROFILES_TABLE;
+
+#pragma pack()
+
+#define EFI_CONFORMANCE_PROFILES_TABLE_VERSION 0x1
+
+//
+// GUID defined in UEFI 2.10
+//
+#define EFI_CONFORMANCE_PROFILES_UEFI_SPEC_GUID \
+ { 0x523c91af, 0xa195, 0x4382, \
+ { 0x81, 0x8d, 0x29, 0x5f, 0xe4, 0x00, 0x64, 0x65 }}
+
+//
+// GUID defined in EBBR
+//
+#define EFI_CONFORMANCE_PROFILE_EBBR_2_1_GUID \
+ { 0xcce33c35, 0x74ac, 0x4087, \
+ { 0xbc, 0xe7, 0x8b, 0x29, 0xb0, 0x2e, 0xeb, 0x27 }}
+#define EFI_CONFORMANCE_PROFILE_EBBR_2_2_GUID \
+ { 0x9073eed4, 0xe50d, 0x11ee, \
+ { 0xb8, 0xb0, 0x8b, 0x68, 0xda, 0x62, 0xfc, 0x80 }}
+
+extern EFI_GUID gEfiConfProfilesTableGuid;
+extern EFI_GUID gEfiConfProfilesUefiSpecGuid;
+
+#endif
diff --git a/MdePkg/Include/IndustryStandard/Acpi51.h b/MdePkg/Include/IndustryStandard/Acpi51.h index 4241b8f..cdf9538 100644 --- a/MdePkg/Include/IndustryStandard/Acpi51.h +++ b/MdePkg/Include/IndustryStandard/Acpi51.h @@ -1760,6 +1760,7 @@ typedef struct { #define EFI_ACPI_5_1_EINJ_EXECUTE_OPERATION 0x05
#define EFI_ACPI_5_1_EINJ_CHECK_BUSY_STATUS 0x06
#define EFI_ACPI_5_1_EINJ_GET_COMMAND_STATUS 0x07
+#define EFI_ACPI_5_1_EINJ_SET_ERROR_TYPE_WITH_ADDRESS 0x08
#define EFI_ACPI_5_1_EINJ_TRIGGER_ERROR 0xFF
///
diff --git a/MdePkg/Include/IndustryStandard/Acpi60.h b/MdePkg/Include/IndustryStandard/Acpi60.h index 3757d3f..d545de1 100644 --- a/MdePkg/Include/IndustryStandard/Acpi60.h +++ b/MdePkg/Include/IndustryStandard/Acpi60.h @@ -1947,6 +1947,7 @@ typedef struct { #define EFI_ACPI_6_0_EINJ_EXECUTE_OPERATION 0x05
#define EFI_ACPI_6_0_EINJ_CHECK_BUSY_STATUS 0x06
#define EFI_ACPI_6_0_EINJ_GET_COMMAND_STATUS 0x07
+#define EFI_ACPI_6_0_EINJ_SET_ERROR_TYPE_WITH_ADDRESS 0x08
#define EFI_ACPI_6_0_EINJ_TRIGGER_ERROR 0xFF
///
diff --git a/MdePkg/Include/IndustryStandard/Acpi61.h b/MdePkg/Include/IndustryStandard/Acpi61.h index c3facc6..5100d8b 100644 --- a/MdePkg/Include/IndustryStandard/Acpi61.h +++ b/MdePkg/Include/IndustryStandard/Acpi61.h @@ -1979,6 +1979,8 @@ typedef struct { #define EFI_ACPI_6_1_EINJ_EXECUTE_OPERATION 0x05
#define EFI_ACPI_6_1_EINJ_CHECK_BUSY_STATUS 0x06
#define EFI_ACPI_6_1_EINJ_GET_COMMAND_STATUS 0x07
+#define EFI_ACPI_6_1_EINJ_SET_ERROR_TYPE_WITH_ADDRESS 0x08
+#define EFI_ACPI_6_1_EINJ_GET_EXECUTE_OPERATION_TIMINGS 0x09
#define EFI_ACPI_6_1_EINJ_TRIGGER_ERROR 0xFF
///
diff --git a/MdePkg/Include/IndustryStandard/Acpi62.h b/MdePkg/Include/IndustryStandard/Acpi62.h index 4dd3e21..711b88b 100644 --- a/MdePkg/Include/IndustryStandard/Acpi62.h +++ b/MdePkg/Include/IndustryStandard/Acpi62.h @@ -2292,6 +2292,8 @@ typedef struct { #define EFI_ACPI_6_2_EINJ_EXECUTE_OPERATION 0x05
#define EFI_ACPI_6_2_EINJ_CHECK_BUSY_STATUS 0x06
#define EFI_ACPI_6_2_EINJ_GET_COMMAND_STATUS 0x07
+#define EFI_ACPI_6_2_EINJ_SET_ERROR_TYPE_WITH_ADDRESS 0x08
+#define EFI_ACPI_6_2_EINJ_GET_EXECUTE_OPERATION_TIMINGS 0x09
#define EFI_ACPI_6_2_EINJ_TRIGGER_ERROR 0xFF
///
diff --git a/MdePkg/Include/IndustryStandard/Acpi63.h b/MdePkg/Include/IndustryStandard/Acpi63.h index 7582dcc..68798da 100644 --- a/MdePkg/Include/IndustryStandard/Acpi63.h +++ b/MdePkg/Include/IndustryStandard/Acpi63.h @@ -2252,6 +2252,8 @@ typedef struct { #define EFI_ACPI_6_3_EINJ_EXECUTE_OPERATION 0x05
#define EFI_ACPI_6_3_EINJ_CHECK_BUSY_STATUS 0x06
#define EFI_ACPI_6_3_EINJ_GET_COMMAND_STATUS 0x07
+#define EFI_ACPI_6_3_EINJ_SET_ERROR_TYPE_WITH_ADDRESS 0x08
+#define EFI_ACPI_6_3_EINJ_GET_EXECUTE_OPERATION_TIMINGS 0x09
#define EFI_ACPI_6_3_EINJ_TRIGGER_ERROR 0xFF
///
diff --git a/MdePkg/Include/IndustryStandard/Acpi64.h b/MdePkg/Include/IndustryStandard/Acpi64.h index faf069a..bbe6a3c 100644 --- a/MdePkg/Include/IndustryStandard/Acpi64.h +++ b/MdePkg/Include/IndustryStandard/Acpi64.h @@ -2335,6 +2335,8 @@ typedef struct { #define EFI_ACPI_6_4_EINJ_EXECUTE_OPERATION 0x05
#define EFI_ACPI_6_4_EINJ_CHECK_BUSY_STATUS 0x06
#define EFI_ACPI_6_4_EINJ_GET_COMMAND_STATUS 0x07
+#define EFI_ACPI_6_4_EINJ_SET_ERROR_TYPE_WITH_ADDRESS 0x08
+#define EFI_ACPI_6_4_EINJ_GET_EXECUTE_OPERATION_TIMINGS 0x09
#define EFI_ACPI_6_4_EINJ_TRIGGER_ERROR 0xFF
///
diff --git a/MdePkg/Include/IndustryStandard/Acpi65.h b/MdePkg/Include/IndustryStandard/Acpi65.h index b9616a3..42a9aaf 100644 --- a/MdePkg/Include/IndustryStandard/Acpi65.h +++ b/MdePkg/Include/IndustryStandard/Acpi65.h @@ -2,7 +2,7 @@ ACPI 6.5 definitions from the ACPI Specification Revision 6.5 Aug, 2022.
Copyright (c) 2017 - 2022, Intel Corporation. All rights reserved.<BR>
- Copyright (c) 2019 - 2023, ARM Ltd. All rights reserved.<BR>
+ Copyright (c) 2019 - 2024, ARM Ltd. All rights reserved.<BR>
Copyright (c) 2023, Loongson Technology Corporation Limited. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -1621,7 +1621,7 @@ typedef struct { #define EFI_ACPI_6_5_NFIT_GUID_BYTE_ADDRESSABLE_PERSISTENT_MEMORY_REGION { 0x66F0D379, 0xB4F3, 0x4074, { 0xAC, 0x43, 0x0D, 0x33, 0x18, 0xB7, 0x8C, 0xDB }}
#define EFI_ACPI_6_5_NFIT_GUID_NVDIMM_CONTROL_REGION { 0x92F701F6, 0x13B4, 0x405D, { 0x91, 0x0B, 0x29, 0x93, 0x67, 0xE8, 0x23, 0x4C }}
#define EFI_ACPI_6_5_NFIT_GUID_NVDIMM_BLOCK_DATA_WINDOW_REGION { 0x91AF0530, 0x5D86, 0x470E, { 0xA6, 0xB0, 0x0A, 0x2D, 0xB9, 0x40, 0x82, 0x49 }}
-#define EFI_ACPI_6_5_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_DISK_REGION_VOLATILE { 0x77AB535A, 0x45FC, 0x6.5B, { 0x55, 0x60, 0xF7, 0xB2, 0x81, 0xD1, 0xF9, 0x6E }}
+#define EFI_ACPI_6_5_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_DISK_REGION_VOLATILE { 0x77AB535A, 0x45FC, 0x624B, { 0x55, 0x60, 0xF7, 0xB2, 0x81, 0xD1, 0xF9, 0x6E }}
#define EFI_ACPI_6_5_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_CD_REGION_VOLATILE { 0x3D5ABD30, 0x4175, 0x87CE, { 0x6D, 0x64, 0xD2, 0xAD, 0xE5, 0x23, 0xC4, 0xBB }}
#define EFI_ACPI_6_5_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_DISK_REGION_PERSISTENT { 0x5CEA02C9, 0x4D07, 0x69D3, { 0x26, 0x9F ,0x44, 0x96, 0xFB, 0xE0, 0x96, 0xF9 }}
#define EFI_ACPI_6_5_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_CD_REGION_PERSISTENT { 0x08018188, 0x42CD, 0xBB48, { 0x10, 0x0F, 0x53, 0x87, 0xD5, 0x3D, 0xED, 0x3D }}
@@ -1949,7 +1949,7 @@ typedef struct { ///
/// HEST Version (as defined in ACPI 6.5 spec.)
///
-#define EFI_ACPI_6_5_HARDWARE_ERROR_SOURCE_TABLE_REVISION 0x01
+#define EFI_ACPI_6_5_HARDWARE_ERROR_SOURCE_TABLE_REVISION 0x02
//
// Error Source structure types.
@@ -2419,7 +2419,7 @@ typedef struct { ///
/// EINJ Version (as defined in ACPI 6.5 spec.)
///
-#define EFI_ACPI_6_5_ERROR_INJECTION_TABLE_REVISION 0x01
+#define EFI_ACPI_6_5_ERROR_INJECTION_TABLE_REVISION 0x02
///
/// EINJ Error Injection Actions
@@ -2432,6 +2432,10 @@ typedef struct { #define EFI_ACPI_6_5_EINJ_EXECUTE_OPERATION 0x05
#define EFI_ACPI_6_5_EINJ_CHECK_BUSY_STATUS 0x06
#define EFI_ACPI_6_5_EINJ_GET_COMMAND_STATUS 0x07
+#define EFI_ACPI_6_5_EINJ_SET_ERROR_TYPE_WITH_ADDRESS 0x08
+#define EFI_ACPI_6_5_EINJ_GET_EXECUTE_OPERATION_TIMINGS 0x09
+#define EFI_ACPI_6_5_EINJ_EINJV2_SET_ERROR_TYPE 0x10
+#define EFI_ACPI_6_5_EINJ_EINJV2_GET_ERROR_TYPE 0x11
#define EFI_ACPI_6_5_EINJ_TRIGGER_ERROR 0xFF
///
@@ -2940,6 +2944,54 @@ typedef struct { #define EFI_ACPI_6_5_PHAT_FIRMWARE_HEALTH_DATA_RECORD_UNKNOWN 0x02
#define EFI_ACPI_6_5_PHAT_FIRMWARE_HEALTH_DATA_RECORD_ADVISORY 0x03
+///
+/// Reset Reason Health Record Vendor Data Entry
+///
+typedef struct {
+ GUID VendorDataID;
+ UINT16 Length;
+ UINT16 Revision;
+ // UINTN Data[];
+} EFI_ACPI_6_5_PHAT_RESET_REASON_HEALTH_RECORD_VENDOR_DATA_ENTRY;
+
+///
+/// Reset Reason Health Record Structure
+///
+typedef struct {
+ UINT8 SupportedSources;
+ UINT8 Source;
+ UINT8 SubSource;
+ UINT8 Reason;
+ UINT16 VendorCount;
+ // EFI_ACPI_6_5_PHAT_RESET_REASON_HEALTH_RECORD_VENDOR_DATA_ENTRY VendorSpecificResetReasonEntry[];
+} EFI_ACPI_6_5_PHAT_RESET_REASON_HEALTH_RECORD_STRUCTURE;
+
+#define EFI_ACPI_6_5_PHAT_RESET_REASON_HEADER_GUID { 0x7a014ce2, 0xf263, 0x4b77, { 0xb8, 0x8a, 0xe6, 0x33, 0x6b, 0x78, 0x2c, 0x14 }}
+
+#define EFI_ACPI_6_5_PHAT_RESET_REASON_SUPPORTED_SOURCES_UNKNOWN BIT0
+#define EFI_ACPI_6_5_PHAT_RESET_REASON_SUPPORTED_SOURCES_HARDWARE BIT1
+#define EFI_ACPI_6_5_PHAT_RESET_REASON_SUPPORTED_SOURCES_FIRMWARE BIT2
+#define EFI_ACPI_6_5_PHAT_RESET_REASON_SUPPORTED_SOURCES_SOFTWARE BIT3
+#define EFI_ACPI_6_5_PHAT_RESET_REASON_SUPPORTED_SOURCES_SUPERVISOR BIT4
+
+#define EFI_ACPI_6_5_PHAT_RESET_REASON_SOURCES_UNKNOWN BIT0
+#define EFI_ACPI_6_5_PHAT_RESET_REASON_SOURCES_HARDWARE BIT1
+#define EFI_ACPI_6_5_PHAT_RESET_REASON_SOURCES_FIRMWARE BIT2
+#define EFI_ACPI_6_5_PHAT_RESET_REASON_SOURCES_SOFTWARE BIT3
+#define EFI_ACPI_6_5_PHAT_RESET_REASON_SOURCES_SUPERVISOR BIT4
+
+#define EFI_ACPI_6_5_PHAT_RESET_REASON_REASON_UNKNOWN 0x00
+#define EFI_ACPI_6_5_PHAT_RESET_REASON_REASON_COLD_BOOT 0x01
+#define EFI_ACPI_6_5_PHAT_RESET_REASON_REASON_COLD_RESET 0x02
+#define EFI_ACPI_6_5_PHAT_RESET_REASON_REASON_WARM_RESET 0x03
+#define EFI_ACPI_6_5_PHAT_RESET_REASON_REASON_UPDATE 0x04
+#define EFI_ACPI_6_5_PHAT_RESET_REASON_REASON_UNEXPECTED_RESET 0x20
+#define EFI_ACPI_6_5_PHAT_RESET_REASON_REASON_FAULT 0x21
+#define EFI_ACPI_6_5_PHAT_RESET_REASON_REASON_TIMEOUT 0x22
+#define EFI_ACPI_6_5_PHAT_RESET_REASON_REASON_THERMAL 0x23
+#define EFI_ACPI_6_5_PHAT_RESET_REASON_REASON_POWER_LOSS 0x24
+#define EFI_ACPI_6_5_PHAT_RESET_REASON_REASON_POWER_BUTTON 0x25
+
//
// Known table signatures
//
@@ -3264,6 +3316,11 @@ typedef struct { ///
#define EFI_ACPI_6_5_XEN_PROJECT_TABLE_SIGNATURE SIGNATURE_32('X', 'E', 'N', 'V')
+///
+/// "MPAM" Memory System Resource Partitioning and Monitoring Table
+///
+#define EFI_ACPI_MEMORY_SYSTEM_RESOURCE_PARTITIONING_AND_MONITORING_TABLE_SIGNATURE SIGNATURE_32('M', 'P', 'A', 'M')
+
#pragma pack()
#endif
diff --git a/MdePkg/Include/IndustryStandard/IoRemappingTable.h b/MdePkg/Include/IndustryStandard/IoRemappingTable.h index 544aa67..851ce00 100644 --- a/MdePkg/Include/IndustryStandard/IoRemappingTable.h +++ b/MdePkg/Include/IndustryStandard/IoRemappingTable.h @@ -43,8 +43,9 @@ #define EFI_ACPI_IORT_MEM_ACCESS_PROP_AH_RA BIT2
#define EFI_ACPI_IORT_MEM_ACCESS_PROP_AH_AHO BIT3
-#define EFI_ACPI_IORT_MEM_ACCESS_FLAGS_CPM BIT0
-#define EFI_ACPI_IORT_MEM_ACCESS_FLAGS_DACS BIT1
+#define EFI_ACPI_IORT_MEM_ACCESS_FLAGS_CPM BIT0
+#define EFI_ACPI_IORT_MEM_ACCESS_FLAGS_DACS BIT1
+#define EFI_ACPI_IORT_MEM_ACCESS_FLAGS_CANWBS BIT2
#define EFI_ACPI_IORT_SMMUv1v2_MODEL_v1 0x0
#define EFI_ACPI_IORT_SMMUv1v2_MODEL_v2 0x1
@@ -60,7 +61,8 @@ #define EFI_ACPI_IORT_SMMUv1v2_INT_FLAG_EDGE 0x1
#define EFI_ACPI_IORT_SMMUv3_FLAG_COHAC_OVERRIDE BIT0
-#define EFI_ACPI_IORT_SMMUv3_FLAG_HTTU_OVERRIDE BIT1
+#define EFI_ACPI_IORT_SMMUv3_FLAG_HTTU_OVERRIDE BIT1 // HW update of Access Flag supported
+#define EFI_ACPI_IORT_SMMUv3_FLAG_HTTU_OVERRIDE_DS BIT2 // HW update of Access Flag + Dirty Flag supported
#define EFI_ACPI_IORT_SMMUv3_FLAG_PROXIMITY_DOMAIN BIT3
#define EFI_ACPI_IORT_SMMUv3_FLAG_DEVICEID_VALID BIT4
diff --git a/MdePkg/Include/IndustryStandard/IpmiNetFnGroupExtension.h b/MdePkg/Include/IndustryStandard/IpmiNetFnGroupExtension.h index 6b26656..aa242ef 100644 --- a/MdePkg/Include/IndustryStandard/IpmiNetFnGroupExtension.h +++ b/MdePkg/Include/IndustryStandard/IpmiNetFnGroupExtension.h @@ -2,12 +2,15 @@ IPMI 2.0 definitions from the IPMI Specification Version 2.0, Revision 1.1.
Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2024, Ampere Computing LLC. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef _IPMI_NET_FN_GROUP_EXTENSION_H_
#define _IPMI_NET_FN_GROUP_EXTENSION_H_
+#include <Pi/PiStatusCode.h>
+
//
// Net function definition for Group Extension command
//
@@ -17,4 +20,70 @@ // All Group Extension commands and their structure definitions to follow here
//
+///
+/// Constants and structure definitions for Boot Progress Codes
+///
+/// See Section F of the Arm Server Base Manageability Requirements 2.0 specification,
+/// https://developer.arm.com/documentation/den0069
+///
+
+//
+// Definitions for send progress code command
+//
+#define IPMI_GROUP_EXTENSION_BOOT_PROGRESS_CODE_SEND 0x02
+
+//
+// Definitions for get progress code command
+//
+#define IPMI_GROUP_EXTENSION_BOOT_PROGRESS_CODE_GET 0x03
+
+//
+// Definitions for send and get progress code command response
+//
+#define IPMI_GROUP_EXTENSION_BOOT_PROGRESS_CODE_COMPLETED_NORMALLY 0x00
+#define IPMI_GROUP_EXTENSION_BOOT_PROGRESS_CODE_COMPLETED_ERROR 0x80
+#define IPMI_GROUP_EXTENSION_BOOT_PROGRESS_CODE_DEFINING_BODY 0xAE
+
+//
+// Structure for the format of the boot progress code data
+// See Table 29: SBMR Boot Progress Codes format
+//
+typedef struct {
+ EFI_STATUS_CODE_TYPE CodeType;
+ EFI_STATUS_CODE_VALUE CodeValue;
+ UINT8 Instance;
+} IPMI_GROUP_EXTENSION_BOOT_PROGRESS_CODE_FORMAT;
+
+//
+// Structure for the boot progress code send request
+//
+typedef struct {
+ UINT8 DefiningBody;
+ IPMI_GROUP_EXTENSION_BOOT_PROGRESS_CODE_FORMAT BootProgressCode;
+} IPMI_GROUP_EXTENSION_BOOT_PROGRESS_CODE_SEND_REQUEST;
+
+//
+// Structure for the boot progress code send response
+//
+typedef struct {
+ UINT8 CompletionCode;
+ UINT8 DefiningBody;
+} IPMI_GROUP_EXTENSION_BOOT_PROGRESS_CODE_SEND_RESPONSE;
+
+//
+// Structure for the boot progress code get request
+//
+typedef struct {
+ UINT8 DefiningBody;
+} IPMI_GROUP_EXTENSION_BOOT_PROGRESS_CODE_GET_REQUEST;
+
+//
+// Structure for the boot progress code get response
+//
+typedef struct {
+ UINT8 CompletionCode;
+ UINT8 DefiningBody;
+ IPMI_GROUP_EXTENSION_BOOT_PROGRESS_CODE_FORMAT BootProgressCode;
+} IPMI_GROUP_EXTENSION_BOOT_PROGRESS_CODE_GET_RESPONSE;
+
#endif
diff --git a/MdePkg/Include/IndustryStandard/Mpam.h b/MdePkg/Include/IndustryStandard/Mpam.h new file mode 100644 index 0000000..8358b35 --- /dev/null +++ b/MdePkg/Include/IndustryStandard/Mpam.h @@ -0,0 +1,246 @@ +/** @file
+ ACPI for Memory System Resource Partitioning and Monitoring 2.0 (MPAM) as
+ specified in ARM spec DEN0065
+
+ Copyright (c) 2024, Arm Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Specification Reference:
+ - [1] ACPI for Memory System Resource Partitioning and Monitoring 2.0
+ (https://developer.arm.com/documentation/den0065/latest)
+
+ @par Glossary:
+ - MPAM - Memory System Resource Partitioning And Monitoring
+ - MSC - Memory System Component
+ - PCC - Platform Communication Channel
+ - RIS - Resource Instance Selection
+ - SMMU - Arm System Memory Management Unit
+ **/
+
+#ifndef MPAM_H_
+#define MPAM_H_
+
+#include <IndustryStandard/Acpi.h>
+
+///
+/// MPAM Revision
+///
+#define EFI_ACPI_MEMORY_SYSTEM_RESOURCE_PARTITIONING_AND_MONITORING_TABLE_REVISION (0x01)
+
+///
+/// MPAM Interrupt mode
+///
+#define EFI_ACPI_MPAM_INTERRUPT_LEVEL_TRIGGERED (0x0)
+#define EFI_ACPI_MPAM_INTERRUPT_EDGE_TRIGGERED (0x1)
+
+///
+/// MPAM Interrupt type
+///
+#define EFI_ACPI_MPAM_INTERRUPT_WIRED (0x0)
+
+///
+/// MPAM Interrupt affinity type
+///
+#define EFI_ACPI_MPAM_INTERRUPT_PROCESSOR_AFFINITY (0x0)
+#define EFI_ACPI_MPAM_INTERRUPT_PROCESSOR_CONTAINER_AFFINITY (0x1)
+
+///
+/// MPAM MSC affinity valid
+///
+#define EFI_ACPI_MPAM_INTERRUPT_AFFINITY_NOT_VALID (0x0)
+#define EFI_ACPI_MPAM_INTERRUPT_AFFINITY_VALID (0x1)
+
+///
+/// MPAM Interrupt flag - bit positions
+///
+#define EFI_ACPI_MPAM_INTERRUPT_MODE_SHIFT (0)
+#define EFI_ACPI_MPAM_INTERRUPT_TYPE_SHIFT (1)
+#define EFI_ACPI_MPAM_INTERRUPT_AFFINITY_TYPE_SHIFT (3)
+#define EFI_ACPI_MPAM_INTERRUPT_AFFINITY_VALID_SHIFT (4)
+#define EFI_ACPI_MPAM_INTERRUPT_RESERVED_SHIFT (5)
+
+///
+/// MPAM Interrupt flag - bit masks
+///
+#define EFI_ACPI_MPAM_INTERRUPT_MODE_MASK (0x1)
+#define EFI_ACPI_MPAM_INTERRUPT_TYPE_MASK (0x3)
+#define EFI_ACPI_MPAM_INTERRUPT_AFFINITY_TYPE_MASK (0x8)
+#define EFI_ACPI_MPAM_INTERRUPT_AFFINITY_VALID_MASK (0x10)
+#define EFI_ACPI_MPAM_INTERRUPT_RESERVED_MASK (0xFFFFFFE0)
+
+///
+/// MPAM Location types
+/// as described in document [1], table 11.
+///
+#define EFI_ACPI_MPAM_LOCATION_PROCESSOR_CACHE (0x0)
+#define EFI_ACPI_MPAM_LOCATION_MEMORY (0x1)
+#define EFI_ACPI_MPAM_LOCATION_SMMU (0x2)
+#define EFI_ACPI_MPAM_LOCATION_MEMORY_CACHE (0x3)
+#define EFI_ACPI_MPAM_LOCATION_ACPI_DEVICE (0x4)
+#define EFI_ACPI_MPAM_LOCATION_INTERCONNECT (0x5)
+#define EFI_ACPI_MPAM_LOCATION_UNKNOWN (0xFF)
+
+///
+/// MPAM Interface types
+/// as desscribed in document[1], table 4.
+///
+#define EFI_ACPI_MPAM_INTERFACE_MMIO (0x00)
+#define EFI_ACPI_MPAM_INTERFACE_PCC (0x0A)
+
+///
+/// MPAM Link types
+/// as described in document [1], table 19.
+///
+#define EFI_ACPI_MPAM_LINK_TYPE_NUMA (0x00)
+#define EFI_ACPI_MPAM_LINK_TYPE_PROC (0x01)
+
+#pragma pack(1)
+
+///
+/// MPAM MSC generic locator descriptor
+/// as described in document [1], table 12.
+///
+typedef struct {
+ UINT64 Descriptor1;
+ UINT32 Descriptor2;
+} EFI_ACPI_MPAM_GENERIC_LOCATOR;
+
+///
+/// MPAM processor cache locator descriptor
+/// as described in document [1], table 13.
+///
+typedef struct {
+ UINT64 CacheReference;
+ UINT32 Reserved;
+} EFI_ACPI_MPAM_CACHE_LOCATOR;
+
+///
+/// MPAM memory locator descriptor
+/// as described in document [1], table 14.
+///
+typedef struct {
+ UINT64 ProximityDomain;
+ UINT32 Reserved;
+} EFI_ACPI_MPAM_MEMORY_LOCATOR;
+
+///
+/// MPAM SMMU locator descriptor
+/// as described in document [1], table 15.
+///
+typedef struct {
+ UINT64 SmmuInterface;
+ UINT32 Reserved;
+} EFI_ACPI_MPAM_SMMU_LOCATOR;
+
+///
+/// MPAM memory-side cache locator descriptor
+/// as described in Document [1], table 16.
+///
+typedef struct {
+ UINT8 Reserved[7];
+ UINT8 Level;
+ UINT32 Reference;
+} EFI_ACPI_MPAM_MEMORY_CACHE_LOCATOR;
+
+///
+/// MPAM ACPI device locator descriptor
+/// as described in document [1], table 17.
+///
+typedef struct {
+ UINT64 AcpiHardwareId;
+ UINT32 AcpiUniqueId;
+} EFI_ACPI_MPAM_ACPI_LOCATOR;
+
+///
+/// MPAM interconnect locator descriptor
+/// as described in document [1], table 18.
+///
+typedef struct {
+ UINT64 InterconnectDescTblOff;
+ UINT32 Reserved;
+} EFI_ACPI_MPAM_INTERCONNECT_LOCATOR;
+
+///
+/// MPAM interconnect descriptor
+/// as described in document [1], table 19.
+///
+typedef struct {
+ UINT32 SourceId;
+ UINT32 DestinationId;
+ UINT8 LinkType;
+ UINT8 Reserved[3];
+} EFI_ACPI_MPAM_INTERCONNECT_DESCRIPTOR;
+
+///
+/// MPAM interconnect descriptor table
+/// as described in document [1], table 20.
+///
+typedef struct {
+ UINT8 Signature[16];
+ UINT32 NumDescriptors;
+} EFI_ACPI_MPAM_INTERCONNECT_DESCRIPTOR_TABLE;
+
+///
+/// MPAM resource locator
+///
+typedef union {
+ EFI_ACPI_MPAM_CACHE_LOCATOR CacheLocator;
+ EFI_ACPI_MPAM_MEMORY_LOCATOR MemoryLocator;
+ EFI_ACPI_MPAM_SMMU_LOCATOR SmmuLocator;
+ EFI_ACPI_MPAM_MEMORY_CACHE_LOCATOR MemCacheLocator;
+ EFI_ACPI_MPAM_ACPI_LOCATOR AcpiLocator;
+ EFI_ACPI_MPAM_INTERCONNECT_LOCATOR InterconnectIfcLocator;
+ EFI_ACPI_MPAM_GENERIC_LOCATOR GenericLocator;
+} EFI_ACPI_MPAM_LOCATOR;
+
+///
+/// MPAM MSC node body
+/// as described document [1], table 4.
+///
+typedef struct {
+ UINT16 Length;
+ UINT8 InterfaceType;
+ UINT8 Reserved;
+ UINT32 Identifier;
+ UINT64 BaseAddress;
+ UINT32 MmioSize;
+ UINT32 OverflowInterrupt;
+ UINT32 OverflowInterruptFlags;
+ UINT32 Reserved1;
+ UINT32 OverflowInterruptAffinity;
+ UINT32 ErrorInterrupt;
+ UINT32 ErrorInterruptFlags;
+ UINT32 Reserved2;
+ UINT32 ErrorInterruptAffinity;
+ UINT32 MaxNrdyUsec;
+ UINT64 HardwareIdLinkedDevice;
+ UINT32 InstanceIdLinkedDevice;
+ UINT32 NumResources;
+} EFI_ACPI_MPAM_MSC_NODE;
+
+///
+/// MPAM MSC resource
+/// as described in document [1], table 9.
+///
+typedef struct {
+ UINT32 Identifier;
+ UINT8 RisIndex;
+ UINT16 Reserved1;
+ UINT8 LocatorType;
+ EFI_ACPI_MPAM_LOCATOR Locator;
+ UINT32 NumFunctionalDependencies;
+} EFI_ACPI_MPAM_MSC_RESOURCE;
+
+///
+/// MPAM Function dependency descriptor
+/// as described in document [1], table 10.
+///
+typedef struct {
+ UINT32 Producer;
+ UINT32 Reserved;
+} EFI_ACPI_MPAM_FUNCTIONAL_DEPENDENCY_DESCRIPTOR;
+
+#pragma pack()
+
+#endif
diff --git a/MdePkg/Include/IndustryStandard/Nvme.h b/MdePkg/Include/IndustryStandard/Nvme.h index 2a94e21..ffb8b84 100644 --- a/MdePkg/Include/IndustryStandard/Nvme.h +++ b/MdePkg/Include/IndustryStandard/Nvme.h @@ -3,6 +3,7 @@ (C) Copyright 2016 Hewlett Packard Enterprise Development LP<BR>
Copyright (c) 2017 - 2023, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) Microsoft Corporation.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@par Specification Reference:
@@ -27,10 +28,12 @@ #define NVME_INTMC_OFFSET 0x0010 // Interrupt Mask Clear
#define NVME_CC_OFFSET 0x0014 // Controller Configuration
#define NVME_CSTS_OFFSET 0x001c // Controller Status
-#define NVME_NSSR_OFFSET 0x0020 // NVM Subsystem Reset
+#define NVME_NSSR_OFFSET 0x0020 // NVM Subsystem Reset (Optional)
#define NVME_AQA_OFFSET 0x0024 // Admin Queue Attributes
#define NVME_ASQ_OFFSET 0x0028 // Admin Submission Queue Base Address
#define NVME_ACQ_OFFSET 0x0030 // Admin Completion Queue Base Address
+#define NVME_CMBLOC_OFFSET 0x0038 // Control Memory Buffer Location (Optional)
+#define NVME_CMBSZ_OFFSET 0x003C // Control Memory Buffer Size (Optional)
#define NVME_BPINFO_OFFSET 0x0040 // Boot Partition Information
#define NVME_BPRSEL_OFFSET 0x0044 // Boot Partition Read Select
#define NVME_BPMBL_OFFSET 0x0048 // Boot Partition Memory Buffer Location
@@ -382,7 +385,21 @@ typedef struct { UINT8 Cmic; /* Multi-interface Capabilities */
UINT8 Mdts; /* Maximum Data Transfer Size */
UINT8 Cntlid[2]; /* Controller ID */
- UINT8 Rsvd1[176]; /* Reserved as of Nvm Express 1.1 Spec */
+ UINT32 Ver; /* Version */
+ UINT32 Rtd3r; /* RTD3 Resume Latency */
+ UINT32 Rtd3e; /* RTD3 Entry Latency */
+ UINT32 Oaes; /* Optional Async Events Supported */
+ UINT32 Ctratt; /* Controller Attributes */
+ UINT16 Rrls; /* Read Recovery Levels Supported */
+ UINT8 Rsvd1[9]; /* Reserved as of NVM Express 1.4c Spec */
+ UINT8 Cntrltype; /* Controller Type */
+ UINT8 Fguid[16]; /* FRU Globally Unique Identifier */
+ UINT16 Crdt1; /* Command Retry Delay Time 1 */
+ UINT16 Crdt2; /* Command Retry Delay Time 2 */
+ UINT16 Crdt3; /* Command Retry Delay Time 3 */
+ UINT8 Rsvd2[106]; /* Reserved as of NVM Express 1.4c Spec */
+ UINT8 Rsvd3[16]; /* Reserved for NVMe MI Spec */
+
//
// Admin Command Set Attributes
//
@@ -418,30 +435,39 @@ typedef struct { UINT16 Mntmt; /* Minimum Thermal Management Temperature */
UINT16 Mxtmt; /* Maximum Thermal Management Temperature */
NVME_SANICAP Sanicap; /* Sanitize Capabilities */
- UINT8 Rsvd2[180]; /* Reserved as of Nvm Express 1.4 Spec */
+ UINT32 Hmminds; /* Host Memory Buffer Minimum Descriptor Entry Size */
+ UINT16 Hmmaxd; /* Host Memory Maximum Descriptors Entries */
+ UINT16 Nsetidmax; /* NVM Set Identifier Maximum */
+ UINT16 Endgidmax; /* Endurance Group Identifier Maximum */
+ UINT8 Anatt; /* ANA Transition Time */
+ UINT8 Anacap; /* Asymmetric Namespace Access Capabilities */
+ UINT32 Anagrpmax; /* ANA Group Identifier Maximum */
+ UINT32 Nanagrpid; /* Number of ANA Group Identifiers */
+ UINT32 Pels; /* Persistent Event Log Size */
+ UINT8 Rsvd4[156]; /* Reserved as of NVM Express 1.4c Spec */
//
// NVM Command Set Attributes
//
- UINT8 Sqes; /* Submission Queue Entry Size */
- UINT8 Cqes; /* Completion Queue Entry Size */
- UINT16 Rsvd3; /* Reserved as of Nvm Express 1.1 Spec */
- UINT32 Nn; /* Number of Namespaces */
- UINT16 Oncs; /* Optional NVM Command Support */
- UINT16 Fuses; /* Fused Operation Support */
- UINT8 Fna; /* Format NVM Attributes */
- UINT8 Vwc; /* Volatile Write Cache */
- UINT16 Awun; /* Atomic Write Unit Normal */
- UINT16 Awupf; /* Atomic Write Unit Power Fail */
- UINT8 Nvscc; /* NVM Vendor Specific Command Configuration */
- UINT8 Rsvd4; /* Reserved as of Nvm Express 1.1 Spec */
- UINT16 Acwu; /* Atomic Compare & Write Unit */
- UINT16 Rsvd5; /* Reserved as of Nvm Express 1.1 Spec */
- UINT32 Sgls; /* SGL Support */
- UINT8 Rsvd6[164]; /* Reserved as of Nvm Express 1.1 Spec */
- //
- // I/O Command set Attributes
- //
- UINT8 Rsvd7[1344]; /* Reserved as of Nvm Express 1.1 Spec */
+ UINT8 Sqes; /* Submission Queue Entry Size */
+ UINT8 Cqes; /* Completion Queue Entry Size */
+ UINT16 Maxcmd; /* Maximum Outstanding Commands */
+ UINT32 Nn; /* Number of Namespaces */
+ UINT16 Oncs; /* Optional NVM Command Support */
+ UINT16 Fuses; /* Fused Operation Support */
+ UINT8 Fna; /* Format NVM Attributes */
+ UINT8 Vwc; /* Volatile Write Cache */
+ UINT16 Awun; /* Atomic Write Unit Normal */
+ UINT16 Awupf; /* Atomic Write Unit Power Fail */
+ UINT8 Nvscc; /* NVM Vendor Specific Command Configuration */
+ UINT8 Nwpc; /* Namespace Write Protection Capabilities */
+ UINT16 Acwu; /* Atomic Compare & Write Unit */
+ UINT16 Rsvd5; /* Reserved as of NVM Express 1.4c Spec */
+ UINT32 Sgls; /* SGL Support */
+ UINT32 Mnan; /* Maximum Number of Allowed Namespace */
+ UINT8 Rsvd6[224]; /* Reserved as of NVM Express 1.4c Spec */
+ UINT8 Subnqn[256]; /* NVM Subsystem NVMe Qualified Name */
+ UINT8 Rsvd7[768]; /* Reserved as of NVM Express 1.4c Spec */
+ UINT8 Rsvd8[256]; /* Reserved for NVMe over Fabrics Spec */
//
// Power State Descriptors
//
@@ -764,6 +790,10 @@ typedef struct { UINT32 Rsvd1 : 20;
} NVME_ADMIN_FORMAT_NVM;
+#define SES_NO_SECURE_ERASE 0x0
+#define SES_USER_DATA_ERASE 0x1
+#define SES_CRYPTO_ERASE 0x2
+
//
// NvmExpress Admin Security Receive Command
//
diff --git a/MdePkg/Include/IndustryStandard/Pci.h b/MdePkg/Include/IndustryStandard/Pci.h index 42c00ac..4220ad8 100644 --- a/MdePkg/Include/IndustryStandard/Pci.h +++ b/MdePkg/Include/IndustryStandard/Pci.h @@ -9,7 +9,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #ifndef _PCI_H_
#define _PCI_H_
-#include <IndustryStandard/PciExpress50.h>
+#include <IndustryStandard/PciExpress60.h>
#include <IndustryStandard/PciCodeId.h>
#endif
diff --git a/MdePkg/Include/IndustryStandard/PciExpress21.h b/MdePkg/Include/IndustryStandard/PciExpress21.h index 341e3e5..b437ca5 100644 --- a/MdePkg/Include/IndustryStandard/PciExpress21.h +++ b/MdePkg/Include/IndustryStandard/PciExpress21.h @@ -40,7 +40,7 @@ typedef union { UINT16 SlotImplemented : 1;
UINT16 InterruptMessageNumber : 5;
UINT16 Undefined : 1;
- UINT16 Reserved : 1;
+ UINT16 FlitModeSupported : 1;
} Bits;
UINT16 Uint16;
} PCI_REG_PCIE_CAPABILITY;
@@ -64,11 +64,13 @@ typedef union { UINT32 EndpointL1AcceptableLatency : 3;
UINT32 Undefined : 3;
UINT32 RoleBasedErrorReporting : 1;
- UINT32 Reserved : 2;
+ UINT32 ErrCorSubclassCapable : 1;
+ UINT32 RxMpsFixed : 1;
UINT32 CapturedSlotPowerLimitValue : 8;
UINT32 CapturedSlotPowerLimitScale : 2;
UINT32 FunctionLevelReset : 1;
- UINT32 Reserved2 : 3;
+ UINT32 MixedMpsSupported : 1;
+ UINT32 Reserved2 : 2;
} Bits;
UINT32 Uint32;
} PCI_REG_PCIE_DEVICE_CAPABILITY;
@@ -111,13 +113,14 @@ typedef union { typedef union {
struct {
- UINT16 CorrectableError : 1;
- UINT16 NonFatalError : 1;
- UINT16 FatalError : 1;
- UINT16 UnsupportedRequest : 1;
- UINT16 AuxPower : 1;
- UINT16 TransactionsPending : 1;
- UINT16 Reserved : 10;
+ UINT16 CorrectableError : 1;
+ UINT16 NonFatalError : 1;
+ UINT16 FatalError : 1;
+ UINT16 UnsupportedRequest : 1;
+ UINT16 AuxPower : 1;
+ UINT16 TransactionsPending : 1;
+ UINT16 EmergencyPowerReductionDetected : 1;
+ UINT16 Reserved : 9;
} Bits;
UINT16 Uint16;
} PCI_REG_PCIE_DEVICE_STATUS;
@@ -146,7 +149,7 @@ typedef union { typedef union {
struct {
UINT16 AspmControl : 2;
- UINT16 Reserved : 1;
+ UINT16 PtmPropagationDelayB : 1;
UINT16 ReadCompletionBoundary : 1;
UINT16 LinkDisable : 1;
UINT16 RetrainLink : 1;
@@ -156,6 +159,9 @@ typedef union { UINT16 HardwareAutonomousWidthDisable : 1;
UINT16 LinkBandwidthManagementInterrupt : 1;
UINT16 LinkAutonomousBandwidthInterrupt : 1;
+ UINT16 SrisClocking : 1;
+ UINT16 FlitModeDisable : 1;
+ UINT16 DrsSignalingControl : 2;
} Bits;
UINT16 Uint16;
} PCI_REG_PCIE_LINK_CONTROL;
@@ -205,7 +211,9 @@ typedef union { UINT16 PowerController : 1;
UINT16 ElectromechanicalInterlock : 1;
UINT16 DataLinkLayerStateChanged : 1;
- UINT16 Reserved : 3;
+ UINT16 AutoSlotPowerLimitDisable : 1;
+ UINT16 InbandPdDisable : 1;
+ UINT16 Reserved : 1;
} Bits;
UINT16 Uint16;
} PCI_REG_PCIE_SLOT_CONTROL;
@@ -233,7 +241,8 @@ typedef union { UINT16 SystemErrorOnFatalError : 1;
UINT16 PmeInterrupt : 1;
UINT16 CrsSoftwareVisibility : 1;
- UINT16 Reserved : 11;
+ UINT16 NoNfmSubtree : 1;
+ UINT16 Reserved : 10;
} Bits;
UINT16 Uint16;
} PCI_REG_PCIE_ROOT_CONTROL;
@@ -268,7 +277,7 @@ typedef union { UINT32 NoRoEnabledPrPrPassing : 1;
UINT32 LtrMechanism : 1;
UINT32 TphCompleter : 2;
- UINT32 LnSystemCLS : 2;
+ UINT32 Reserved : 2;
UINT32 TenBitTagCompleterSupported : 1;
UINT32 TenBitTagRequesterSupported : 1;
UINT32 Obff : 2;
@@ -277,7 +286,9 @@ typedef union { UINT32 MaxEndEndTlpPrefixes : 2;
UINT32 EmergencyPowerReductionSupported : 2;
UINT32 EmergencyPowerReductionInitializationRequired : 1;
- UINT32 Reserved3 : 4;
+ UINT32 Reserved2 : 1;
+ UINT32 DmwrCompleter : 1;
+ UINT32 DmwrLengths : 2;
UINT32 FrsSupported : 1;
} Bits;
UINT32 Uint32;
@@ -330,10 +341,15 @@ typedef union { typedef union {
struct {
- UINT32 Reserved : 1;
- UINT32 LinkSpeedsVector : 7;
- UINT32 Crosslink : 1;
- UINT32 Reserved2 : 23;
+ UINT32 Reserved : 1;
+ UINT32 LinkSpeedsVector : 7;
+ UINT32 Crosslink : 1;
+ UINT32 LowerSkpOsGeneration : 7;
+ UINT32 LowerSkpOsReception : 7;
+ UINT32 RetimerPresenceDetect : 1;
+ UINT32 TwoRetimersPresenceDetect : 1;
+ UINT32 Reserved2 : 6;
+ UINT32 DrsSupported : 1;
} Bits;
UINT32 Uint32;
} PCI_REG_PCIE_LINK_CAPABILITY2;
@@ -360,11 +376,25 @@ typedef union { UINT16 EqualizationPhase2Successful : 1;
UINT16 EqualizationPhase3Successful : 1;
UINT16 LinkEqualizationRequest : 1;
- UINT16 Reserved : 10;
+ UINT16 RetimerPresence : 1;
+ UINT16 TwoRetimersPresence : 1;
+ UINT16 CrosslinkResolution : 2;
+ UINT16 FlitModeStatus : 1;
+ UINT16 Reserved : 1;
+ UINT16 DownstreamComponentPresence : 3;
+ UINT16 DRSMessageReceived : 1;
} Bits;
UINT16 Uint16;
} PCI_REG_PCIE_LINK_STATUS2;
+typedef union {
+ struct {
+ UINT32 InbandPdDisable : 1;
+ UINT32 Reserved : 30;
+ } Bits;
+ UINT32 Uint32;
+} PCI_REG_PCIE_SLOT_CAPABILITY2;
+
typedef struct {
EFI_PCI_CAPABILITY_HDR Hdr;
PCI_REG_PCIE_CAPABILITY Capability;
@@ -386,7 +416,7 @@ typedef struct { PCI_REG_PCIE_LINK_CAPABILITY2 LinkCapability2;
PCI_REG_PCIE_LINK_CONTROL2 LinkControl2;
PCI_REG_PCIE_LINK_STATUS2 LinkStatus2;
- UINT32 SlotCapability2;
+ PCI_REG_PCIE_SLOT_CAPABILITY2 SlotCapability2;
UINT16 SlotControl2;
UINT16 SlotStatus2;
} PCI_CAPABILITY_PCIEXP;
diff --git a/MdePkg/Include/IndustryStandard/PciExpress60.h b/MdePkg/Include/IndustryStandard/PciExpress60.h new file mode 100644 index 0000000..5427ddd --- /dev/null +++ b/MdePkg/Include/IndustryStandard/PciExpress60.h @@ -0,0 +1,121 @@ +/** @file
+Support for the PCI Express 6.0 standard.
+
+This header file may not define all structures. Please extend as required.
+
+Copyright (c) 2024, American Megatrends International LLC. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef PCIEXPRESS60_H_
+#define PCIEXPRESS60_H_
+
+#include <IndustryStandard/PciExpress50.h>
+
+/// The Physical Layer PCI Express Extended Capability definitions.
+///
+/// Based on section 7.7.7 of PCI Express Base Specification 6.0.
+///@{
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_PHYSICAL_LAYER_64_0_ID 0x0031
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_PHYSICAL_LAYER_64_0_VER1 0x1
+
+// Register offsets from Physical Layer PCI-E Ext Cap Header
+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_64_0_CAPABILITIES_OFFSET 0x04
+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_64_0_CONTROL_OFFSET 0x08
+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_64_0_STATUS_OFFSET 0x0C
+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_64_0_LANE_EQUALIZATION_CONTROL_OFFSET 0x10
+
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_DEVICE3_ID 0x002F
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_DEVICE3_VER1 0x1
+
+#define EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_3_OFFSET 0x04
+#define EFI_PCIE_CAPABILITY_DEVICE_CONTROL_3_OFFSET 0x08
+#define EFI_PCIE_CAPABILITY_DEVICE_STATUS_3_OFFSET 0x0C
+
+#pragma pack(1)
+
+typedef union {
+ struct {
+ UINT32 Reserved : 32; // Reserved bit 0:31
+ } Bits;
+ UINT32 Uint32;
+} PCI_EXPRESS_REG_PHYSICAL_LAYER_64_0_CAPABILITIES;
+
+typedef union {
+ struct {
+ UINT32 Reserved : 32; // Reserved bit 0:31
+ } Bits;
+ UINT32 Uint32;
+} PCI_EXPRESS_REG_PHYSICAL_LAYER_64_0_CONTROL;
+
+typedef union {
+ struct {
+ UINT32 EqualizationComplete : 1; // bit 0
+ UINT32 EqualizationPhase1Success : 1; // bit 1
+ UINT32 EqualizationPhase2Success : 1; // bit 2
+ UINT32 EqualizationPhase3Success : 1; // bit 3
+ UINT32 LinkEqualizationRequest : 1; // bit 4
+ UINT32 TransmitterPrecodingOn : 1; // bit 5
+ UINT32 TransmitterPrecodeRequest : 1; // bit 6
+ UINT32 NoEqualizationNeededRcvd : 1; // bit 7
+ UINT32 Reserved : 24; // Reserved bit 8:31
+ } Bits;
+ UINT32 Uint32;
+} PCI_EXPRESS_REG_PHYSICAL_LAYER_64_0_STATUS;
+
+typedef union {
+ struct {
+ UINT8 DownstreamPortTransmitterPreset : 4; // bit 0..3
+ UINT8 UpstreamPortTransmitterPreset : 4; // bit 4..7
+ } Bits;
+ UINT8 Uint8;
+} PCI_EXPRESS_REG_PHYSICAL_LAYER_64_0_LANE_EQUALIZATION_CONTROL;
+
+typedef struct {
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
+ PCI_EXPRESS_REG_PHYSICAL_LAYER_64_0_CAPABILITIES Capablities;
+ PCI_EXPRESS_REG_PHYSICAL_LAYER_64_0_CONTROL Control;
+ PCI_EXPRESS_REG_PHYSICAL_LAYER_64_0_STATUS Status;
+ PCI_EXPRESS_REG_PHYSICAL_LAYER_64_0_LANE_EQUALIZATION_CONTROL LaneEqualizationControl[1];
+} PCI_EXPRESS_EXTENDED_CAPABILITIES_PHYSICAL_LAYER_64_0;
+///@}
+
+typedef union {
+ struct {
+ UINT32 DmwrRequestRouting : 1; // bit 0
+ UINT32 FourteenBitTagCompleter : 1; // bit 1
+ UINT32 FourteenBitTagRequester : 1; // bit 2
+ UINT32 ReceiverL0p : 1; // bit 3
+ UINT32 PortL0pExitLatencyLatency : 3; // bit 4..6
+ UINT32 RetimerL0pExit : 3; // bit 7..9
+ UINT32 Reserved : 22; // bit 10..31
+ } Bits;
+ UINT32 Uint32;
+} PCI_REG_PCIE_DEVICE_CAPABILITY3;
+
+typedef union {
+ struct {
+ UINT32 DmwrRequesterEnable : 1; // bit 0
+ UINT32 DmwrEgressBlocking : 1; // bit 1
+ UINT32 FourteenBitTagRequesterEnable : 1; // bit 2
+ UINT32 L0pEnable : 1; // bit 3
+ UINT32 TargetLinkWidth : 3; // bit 4..6
+ UINT32 Reserved : 25; // bit 7..31
+ } Bits;
+ UINT32 Uint32;
+} PCI_REG_PCIE_DEVICE_CONTROL3;
+
+typedef union {
+ struct {
+ UINT32 InitialLinkWidth : 3; // bit 0..2
+ UINT32 SegmentCaptured : 1; // bit 3
+ UINT32 RemoteL0pSupported : 1; // bit 4
+ UINT32 Reserved : 27; // bit 5..31
+ } Bits;
+ UINT32 Uint32;
+} PCI_REG_PCIE_DEVICE_STATUS3;
+
+#pragma pack()
+
+#endif
diff --git a/MdePkg/Include/IndustryStandard/SmBios.h b/MdePkg/Include/IndustryStandard/SmBios.h index 020733b..8ba6129 100644 --- a/MdePkg/Include/IndustryStandard/SmBios.h +++ b/MdePkg/Include/IndustryStandard/SmBios.h @@ -887,7 +887,8 @@ typedef enum { ProcessorUpgradeSocketBGA2551 = 0x54,
ProcessorUpgradeSocketLGA1851 = 0x55,
ProcessorUpgradeSocketBGA2114 = 0x56,
- ProcessorUpgradeSocketBGA2833 = 0x57
+ ProcessorUpgradeSocketBGA2833 = 0x57,
+ ProcessorUpgradeInvalid = 0xFF
} PROCESSOR_UPGRADE;
///
@@ -1020,6 +1021,10 @@ typedef struct { // Add for smbios 3.6
//
UINT16 ThreadEnabled;
+ //
+ // Add for smbios 3.8
+ //
+ SMBIOS_TABLE_STRING SocketType;
} SMBIOS_TABLE_TYPE4;
///
@@ -1524,7 +1529,7 @@ typedef struct { UINT8 AsyncSurpriseRemoval : 1;
UINT8 FlexbusSlotCxl10Capable : 1;
UINT8 FlexbusSlotCxl20Capable : 1;
- UINT8 Reserved : 1; ///< Set to 0.
+ UINT8 FlexbusSlotCxl30Capable : 1; /// SMBIOS spec 3.7.0 updated CXL 3.0 support
} MISC_SLOT_CHARACTERISTICS2;
///
@@ -2027,6 +2032,13 @@ typedef struct { //
UINT32 ExtendedSpeed;
UINT32 ExtendedConfiguredMemorySpeed;
+ //
+ // Add for smbios 3.7.0
+ //
+ UINT16 Pmic0ManufacturerID;
+ UINT16 Pmic0RevisionNumber;
+ UINT16 RcdManufacturerID;
+ UINT16 RcdRevisionNumber;
} SMBIOS_TABLE_TYPE17;
///
diff --git a/MdePkg/Include/IndustryStandard/Tpm20.h b/MdePkg/Include/IndustryStandard/Tpm20.h index 4440f37..9303f16 100644 --- a/MdePkg/Include/IndustryStandard/Tpm20.h +++ b/MdePkg/Include/IndustryStandard/Tpm20.h @@ -203,15 +203,16 @@ typedef UINT16 TPM_ALG_ID; // Table 8 - TPM_ECC_CURVE Constants
typedef UINT16 TPM_ECC_CURVE;
-#define TPM_ECC_NONE (TPM_ECC_CURVE)(0x0000)
-#define TPM_ECC_NIST_P192 (TPM_ECC_CURVE)(0x0001)
-#define TPM_ECC_NIST_P224 (TPM_ECC_CURVE)(0x0002)
-#define TPM_ECC_NIST_P256 (TPM_ECC_CURVE)(0x0003)
-#define TPM_ECC_NIST_P384 (TPM_ECC_CURVE)(0x0004)
-#define TPM_ECC_NIST_P521 (TPM_ECC_CURVE)(0x0005)
-#define TPM_ECC_BN_P256 (TPM_ECC_CURVE)(0x0010)
-#define TPM_ECC_BN_P638 (TPM_ECC_CURVE)(0x0011)
-#define TPM_ECC_SM2_P256 (TPM_ECC_CURVE)(0x0020)
+#define TPM_ECC_NONE (TPM_ECC_CURVE)(0x0000)
+#define TPM_ECC_NIST_P192 (TPM_ECC_CURVE)(0x0001)
+#define TPM_ECC_NIST_P224 (TPM_ECC_CURVE)(0x0002)
+#define TPM_ECC_NIST_P256 (TPM_ECC_CURVE)(0x0003)
+#define TPM_ECC_NIST_P384 (TPM_ECC_CURVE)(0x0004)
+#define TPM_ECC_NIST_P521 (TPM_ECC_CURVE)(0x0005)
+#define TPM_ECC_BN_P256 (TPM_ECC_CURVE)(0x0010)
+#define TPM_ECC_BN_P638 (TPM_ECC_CURVE)(0x0011)
+#define TPM_ECC_SM2_P256 (TPM_ECC_CURVE)(0x0020)
+#define TPM_ECC_BP_P512_R1 (TPM_ECC_CURVE)(0x0032)
// Table 11 - TPM_CC Constants (Numeric Order)
typedef UINT32 TPM_CC;
diff --git a/MdePkg/Include/IndustryStandard/Tpm2Acpi.h b/MdePkg/Include/IndustryStandard/Tpm2Acpi.h index e7d14f9..882e21d 100644 --- a/MdePkg/Include/IndustryStandard/Tpm2Acpi.h +++ b/MdePkg/Include/IndustryStandard/Tpm2Acpi.h @@ -3,6 +3,7 @@ Copyright (c) 2013 - 2019, Intel Corporation. All rights reserved. <BR>
Copyright (c) 2021, Ampere Computing LLC. All rights reserved. <BR>
+Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. <BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -18,6 +19,9 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #define EFI_TPM2_ACPI_TABLE_REVISION_4 4
#define EFI_TPM2_ACPI_TABLE_REVISION EFI_TPM2_ACPI_TABLE_REVISION_4
+#define EFI_TPM2_ACPI_TABLE_START_METHOD_SPECIFIC_PARAMETERS_MAX_SIZE_REVISION_4 12
+#define EFI_TPM2_ACPI_TABLE_START_METHOD_SPECIFIC_PARAMETERS_MAX_SIZE EFI_TPM2_ACPI_TABLE_START_METHOD_SPECIFIC_PARAMETERS_MAX_SIZE_REVISION_4
+
typedef struct {
EFI_ACPI_DESCRIPTION_HEADER Header;
// Flags field is replaced in version 4 and above
diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/BaseLib.h index 95f8055..eb817f1 100644 --- a/MdePkg/Include/Library/BaseLib.h +++ b/MdePkg/Include/Library/BaseLib.h @@ -7,6 +7,7 @@ Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> Copyright (c) Microsoft Corporation.<BR>
Portions Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
Portions Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.<BR>
+Copyright (c) 2023 - 2024, Arm Limited. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -126,6 +127,92 @@ typedef struct { #define BASE_LIBRARY_JUMP_BUFFER_ALIGNMENT 8
+/**
+ Reads the current value of CNTPCT_EL0 register.
+
+ Reads and returns the current value of CNTPCT_EL0.
+ This function is only available on AARCH64.
+
+ @return The current value of CNTPCT_EL0
+**/
+UINT64
+EFIAPI
+ArmReadCntPctReg (
+ VOID
+ );
+
+//
+// Bit shifts for the ID_AA64ISAR0_EL1 register.
+//
+#define ARM_ID_AA64ISAR0_EL1_AES_SHIFT (4U)
+#define ARM_ID_AA64ISAR0_EL1_SHA1_SHIFT (8U)
+#define ARM_ID_AA64ISAR0_EL1_SHA2_SHIFT (12U)
+#define ARM_ID_AA64ISAR0_EL1_CRC32_SHIFT (16U)
+#define ARM_ID_AA64ISAR0_EL1_ATOMIC_SHIFT (20U)
+#define ARM_ID_AA64ISAR0_EL1_RDM_SHIFT (28U)
+#define ARM_ID_AA64ISAR0_EL1_SHA3_SHIFT (32U)
+#define ARM_ID_AA64ISAR0_EL1_SM3_SHIFT (36U)
+#define ARM_ID_AA64ISAR0_EL1_SM4_SHIFT (40U)
+#define ARM_ID_AA64ISAR0_EL1_DP_SHIFT (44U)
+#define ARM_ID_AA64ISAR0_EL1_FHM_SHIFT (48U)
+#define ARM_ID_AA64ISAR0_EL1_TS_SHIFT (52U)
+#define ARM_ID_AA64ISAR0_EL1_TLB_SHIFT (56U)
+#define ARM_ID_AA64ISAR0_EL1_RNDR_SHIFT (60U)
+
+//
+// Bit masks for the ID_AA64ISAR0_EL1 fields.
+//
+#define ARM_ID_AA64ISAR0_EL1_AES_MASK (0xFU)
+#define ARM_ID_AA64ISAR0_EL1_SHA1_MASK (0xFU)
+#define ARM_ID_AA64ISAR0_EL1_SHA2_MASK (0xFU)
+#define ARM_ID_AA64ISAR0_EL1_CRC32_MASK (0xFU)
+#define ARM_ID_AA64ISAR0_EL1_ATOMIC_MASK (0xFU)
+#define ARM_ID_AA64ISAR0_EL1_RDM_MASK (0xFU)
+#define ARM_ID_AA64ISAR0_EL1_SHA3_MASK (0xFU)
+#define ARM_ID_AA64ISAR0_EL1_SM3_MASK (0xFU)
+#define ARM_ID_AA64ISAR0_EL1_SM4_MASK (0xFU)
+#define ARM_ID_AA64ISAR0_EL1_DP_MASK (0xFU)
+#define ARM_ID_AA64ISAR0_EL1_FHM_MASK (0xFU)
+#define ARM_ID_AA64ISAR0_EL1_TS_MASK (0xFU)
+#define ARM_ID_AA64ISAR0_EL1_TLB_MASK (0xFU)
+#define ARM_ID_AA64ISAR0_EL1_RNDR_MASK (0xFU)
+
+//
+// Bit masks for the ID_AA64ISAR0_EL1 field values.
+//
+#define ARM_ID_AA64ISAR0_EL1_AES_FEAT_AES_MASK (0x1U)
+#define ARM_ID_AA64ISAR0_EL1_AES_FEAT_PMULL_MASK (0x2U)
+#define ARM_ID_AA64ISAR0_EL1_SHA1_FEAT_SHA1_MASK (0x1U)
+#define ARM_ID_AA64ISAR0_EL1_SHA2_FEAT_SHA256_MASK (0x1U)
+#define ARM_ID_AA64ISAR0_EL1_SHA2_FEAT_SHA512_MASK (0x2U)
+#define ARM_ID_AA64ISAR0_EL1_CRC32_HAVE_CRC32_MASK (0x1U)
+#define ARM_ID_AA64ISAR0_EL1_ATOMIC_FEAT_LSE_MASK (0x2U)
+#define ARM_ID_AA64ISAR0_EL1_RDM_FEAT_RDM_MASK (0x1U)
+#define ARM_ID_AA64ISAR0_EL1_SHA3_FEAT_SHA3_MASK (0x1U)
+#define ARM_ID_AA64ISAR0_EL1_SM3_FEAT_SM3_MASK (0x1U)
+#define ARM_ID_AA64ISAR0_EL1_SM4_FEAT_SM4_MASK (0x1U)
+#define ARM_ID_AA64ISAR0_EL1_DP_FEAT_DOTPROD_MASK (0x1U)
+#define ARM_ID_AA64ISAR0_EL1_FHM_FEAT_FHM_MASK (0x1U)
+#define ARM_ID_AA64ISAR0_EL1_TS_FEAT_FLAGM_MASK (0x1U)
+#define ARM_ID_AA64ISAR0_EL1_TS_FEAT_FLAGM2_MASK (0x2U)
+#define ARM_ID_AA64ISAR0_EL1_TLB_FEAT_TLBIOS_MASK (0x1U)
+#define ARM_ID_AA64ISAR0_EL1_TLB_FEAT_TLBIRANGE_MASK (0x2U)
+#define ARM_ID_AA64ISAR0_EL1_RNDR_FEAT_RNG_MASK (0x1U)
+
+/**
+ Reads the current value of ID_AA64ISAR0_EL1 register.
+
+ Reads and returns the current value of ID_AA64ISAR0_EL1.
+ This function is only available on AARCH64.
+
+ @return The current value of ID_AA64ISAR0_EL1
+**/
+UINT64
+EFIAPI
+ArmReadIdAA64Isar0Reg (
+ VOID
+ );
+
#endif // defined (MDE_CPU_AARCH64)
#if defined (MDE_CPU_RISCV64)
@@ -4900,6 +4987,23 @@ CalculateCrc32c ( IN UINT32 InitialValue
);
+/**
+ Calculates the CRC16-CCITT-FALSE checksum of the given buffer.
+
+ @param[in] Buffer Pointer to the buffer.
+ @param[in] Length Length of the buffer, in bytes.
+ @param[in] InitialValue Initial value of the CRC.
+
+ @return The CRC16-CCITT-FALSE checksum.
+**/
+UINT16
+EFIAPI
+CalculateCrc16CcittF (
+ IN CONST VOID *Buffer,
+ IN UINTN Length,
+ IN UINT16 InitialValue
+ );
+
//
// Base Library CPU Functions
//
diff --git a/MdePkg/Include/Library/FdtLib.h b/MdePkg/Include/Library/FdtLib.h index 65d7460..89aa1e0 100644 --- a/MdePkg/Include/Library/FdtLib.h +++ b/MdePkg/Include/Library/FdtLib.h @@ -432,4 +432,21 @@ FdtNodeDepth ( IN INT32 NodeOffset
);
+/**
+ Find nodes with a given 'compatible' value.
+
+ @param[in] Fdt The pointer to FDT blob.
+ @param[in] StartOffset Only find nodes after this offset.
+ @param[in] Compatible The string to match against.
+
+ @retval The offset of the first node after StartOffset.
+**/
+INT32
+EFIAPI
+FdtNodeOffsetByCompatible (
+ IN CONST VOID *Fdt,
+ IN INT32 StartOffset,
+ IN CONST CHAR8 *Compatible
+ );
+
#endif /* FDT_LIB_H_ */
diff --git a/MdePkg/Include/Protocol/Http.h b/MdePkg/Include/Protocol/Http.h index 28e6221..7d9481a 100644 --- a/MdePkg/Include/Protocol/Http.h +++ b/MdePkg/Include/Protocol/Http.h @@ -98,7 +98,8 @@ typedef enum { HTTP_STATUS_503_SERVICE_UNAVAILABLE,
HTTP_STATUS_504_GATEWAY_TIME_OUT,
HTTP_STATUS_505_HTTP_VERSION_NOT_SUPPORTED,
- HTTP_STATUS_308_PERMANENT_REDIRECT
+ HTTP_STATUS_308_PERMANENT_REDIRECT,
+ HTTP_STATUS_429_TOO_MANY_REQUESTS
} EFI_HTTP_STATUS_CODE;
///
diff --git a/MdePkg/Include/Protocol/Smbios.h b/MdePkg/Include/Protocol/Smbios.h index f9346aa..e6977b4 100644 --- a/MdePkg/Include/Protocol/Smbios.h +++ b/MdePkg/Include/Protocol/Smbios.h @@ -69,6 +69,10 @@ #define EFI_SMBIOS_TYPE_ADDITIONAL_INFORMATION SMBIOS_TYPE_ADDITIONAL_INFORMATION
#define EFI_SMBIOS_TYPE_ONBOARD_DEVICES_EXTENDED_INFORMATION SMBIOS_TYPE_ONBOARD_DEVICES_EXTENDED_INFORMATION
#define EFI_SMBIOS_TYPE_MANAGEMENT_CONTROLLER_HOST_INTERFACE SMBIOS_TYPE_MANAGEMENT_CONTROLLER_HOST_INTERFACE
+#define EFI_SMBIOS_TYPE_TPM_DEVICE SMBIOS_TYPE_TPM_DEVICE
+#define EFI_SMBIOS_TYPE_PROCESSOR_ADDITIONAL_INFORMATION SMBIOS_TYPE_PROCESSOR_ADDITIONAL_INFORMATION
+#define EFI_SMBIOS_TYPE_FIRMWARE_INVENTORY_INFORMATION SMBIOS_TYPE_FIRMWARE_INVENTORY_INFORMATION
+#define EFI_SMBIOS_TYPE_STRING_PROPERTY_INFORMATION SMBIOS_TYPE_STRING_PROPERTY_INFORMATION
#define EFI_SMBIOS_TYPE_INACTIVE SMBIOS_TYPE_INACTIVE
#define EFI_SMBIOS_TYPE_END_OF_TABLE SMBIOS_TYPE_END_OF_TABLE
#define EFI_SMBIOS_OEM_BEGIN SMBIOS_OEM_BEGIN
diff --git a/MdePkg/Include/Register/Intel/StmApi.h b/MdePkg/Include/Register/Intel/StmApi.h index 9d42bcd..6c1cdf9 100644 --- a/MdePkg/Include/Register/Intel/StmApi.h +++ b/MdePkg/Include/Register/Intel/StmApi.h @@ -18,6 +18,8 @@ #pragma pack (1)
+#define STM_SMM_REV_ID 0x80010100
+
/**
STM Header Structures
**/
diff --git a/MdePkg/Include/Register/LoongArch64/Csr.h b/MdePkg/Include/Register/LoongArch64/Csr.h index aa22a26..fe2ebd9 100644 --- a/MdePkg/Include/Register/LoongArch64/Csr.h +++ b/MdePkg/Include/Register/LoongArch64/Csr.h @@ -112,7 +112,7 @@ //
// Config CSR registers
//
-#define LOONGARCH_CSR_CPUNUM 0x20 // CPU core number
+#define LOONGARCH_CSR_CPUID 0x20 // CPU core ID
#define LOONGARCH_CSR_PRCFG1 0x21 // Config1
#define LOONGARCH_CSR_PRCFG2 0x22 // Config2
#define LOONGARCH_CSR_PRCFG3 0x23 // Config3
diff --git a/MdePkg/Include/Register/RiscV64/RiscVEncoding.h b/MdePkg/Include/Register/RiscV64/RiscVEncoding.h index 8ccdea2..a656d44 100644 --- a/MdePkg/Include/Register/RiscV64/RiscVEncoding.h +++ b/MdePkg/Include/Register/RiscV64/RiscVEncoding.h @@ -120,4 +120,14 @@ #define CAUSE_VIRTUAL_INST_FAULT 0x16
#define CAUSE_STORE_GUEST_PAGE_FAULT 0x17
+/* Sstc extension */
+#define CSR_SEED 0x15
+
+#define SEED_OPST_MASK 0xc0000000
+#define SEED_OPST_BIST 0x00000000
+#define SEED_OPST_WAIT 0x40000000
+#define SEED_OPST_ES16 0x80000000
+#define SEED_OPST_DEAD 0xc0000000
+#define SEED_ENTROPY_MASK 0xffff
+
#endif
diff --git a/MdePkg/Include/Uefi/UefiMultiPhase.h b/MdePkg/Include/Uefi/UefiMultiPhase.h index 7884913..1f1f3f4 100644 --- a/MdePkg/Include/Uefi/UefiMultiPhase.h +++ b/MdePkg/Include/Uefi/UefiMultiPhase.h @@ -108,7 +108,22 @@ typedef enum { /// by a corresponding call to the underlying isolation architecture.
///
EfiUnacceptedMemoryType,
- EfiMaxMemoryType
+ EfiMaxMemoryType,
+ //
+ // +---------------------------------------------------+
+ // | 0..(EfiMaxMemoryType - 1) - Normal memory type |
+ // +---------------------------------------------------+
+ // | EfiMaxMemoryType..0x6FFFFFFF - Invalid |
+ // +---------------------------------------------------+
+ // | 0x70000000..0x7FFFFFFF - OEM reserved |
+ // +---------------------------------------------------+
+ // | 0x80000000..0xFFFFFFFF - OS reserved |
+ // +---------------------------------------------------+
+ //
+ MEMORY_TYPE_OEM_RESERVED_MIN = 0x70000000,
+ MEMORY_TYPE_OEM_RESERVED_MAX = 0x7FFFFFFF,
+ MEMORY_TYPE_OS_RESERVED_MIN = 0x80000000,
+ MEMORY_TYPE_OS_RESERVED_MAX = 0xFFFFFFFF
} EFI_MEMORY_TYPE;
///
diff --git a/MdePkg/Library/BaseArmTrngLibNull/BaseArmTrngLibNull.c b/MdePkg/Library/BaseArmTrngLibNull/BaseArmTrngLibNull.c index 316d78b..84366a4 100644 --- a/MdePkg/Library/BaseArmTrngLibNull/BaseArmTrngLibNull.c +++ b/MdePkg/Library/BaseArmTrngLibNull/BaseArmTrngLibNull.c @@ -41,7 +41,7 @@ GetArmTrngVersion ( OUT UINT16 *MinorRevision
)
{
- ASSERT (FALSE);
+ DEBUG ((DEBUG_ERROR, "ArmTrng Backend not found\n"));
return RETURN_UNSUPPORTED;
}
diff --git a/MdePkg/Library/BaseFdtLib/BaseFdtLib.inf b/MdePkg/Library/BaseFdtLib/BaseFdtLib.inf index 730e568..b581538 100644 --- a/MdePkg/Library/BaseFdtLib/BaseFdtLib.inf +++ b/MdePkg/Library/BaseFdtLib/BaseFdtLib.inf @@ -57,6 +57,9 @@ BaseMemoryLib
[BuildOptions]
- MSFT:*_*_IA32_CC_FLAGS = /wd4146 /wd4245
- MSFT:*_*_X64_CC_FLAGS = /wd4146 /wd4244 /wd4245 /wd4267
+# warning C4706: assignment within conditional expression
+# if ((err = fdt_splice_(fdt, p, oldlen, newlen)))
+# in BaseFdtLib\libfdt\libfdt\fdt_rw.c (wait for sub module update to remove this)
+ MSFT:*_*_IA32_CC_FLAGS = /wd4146 /wd4245 /wd4706
+ MSFT:*_*_X64_CC_FLAGS = /wd4146 /wd4244 /wd4245 /wd4267 /wd4706
diff --git a/MdePkg/Library/BaseFdtLib/FdtLib.c b/MdePkg/Library/BaseFdtLib/FdtLib.c index c9514af..9b1ceac 100644 --- a/MdePkg/Library/BaseFdtLib/FdtLib.c +++ b/MdePkg/Library/BaseFdtLib/FdtLib.c @@ -442,3 +442,23 @@ FdtNodeDepth ( {
return fdt_node_depth (Fdt, NodeOffset);
}
+
+/**
+ Find nodes with a given 'compatible' value.
+
+ @param[in] Fdt The pointer to FDT blob.
+ @param[in] StartOffset Only find nodes after this offset.
+ @param[in] Compatible The string to match against.
+
+ @retval The offset of the first node after StartOffset.
+**/
+INT32
+EFIAPI
+FdtNodeOffsetByCompatible (
+ IN CONST VOID *Fdt,
+ IN INT32 StartOffset,
+ IN CONST CHAR8 *Compatible
+ )
+{
+ return fdt_node_offset_by_compatible (Fdt, StartOffset, Compatible);
+}
diff --git a/MdePkg/Library/BaseLib/AArch64/ArmReadCntPctReg.S b/MdePkg/Library/BaseLib/AArch64/ArmReadCntPctReg.S new file mode 100644 index 0000000..cfabd7a --- /dev/null +++ b/MdePkg/Library/BaseLib/AArch64/ArmReadCntPctReg.S @@ -0,0 +1,30 @@ +#------------------------------------------------------------------------------
+#
+# ArmReadCntPctReg() for AArch64
+#
+# Copyright (c) 2023 - 2024, Arm Limited. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#------------------------------------------------------------------------------
+
+.text
+.p2align 2
+GCC_ASM_EXPORT(ArmReadCntPctReg)
+
+#/**
+# Reads the CNTPCT_EL0 Register.
+#
+# @return The contents of the CNTPCT_EL0 register.
+#
+#**/
+#UINT64
+#EFIAPI
+#ArmReadCntPctReg (
+# VOID
+# );
+#
+ASM_PFX(ArmReadCntPctReg):
+ AARCH64_BTI(c)
+ mrs x0, cntpct_el0
+ ret
diff --git a/MdePkg/Library/BaseLib/AArch64/ArmReadCntPctReg.asm b/MdePkg/Library/BaseLib/AArch64/ArmReadCntPctReg.asm new file mode 100644 index 0000000..98823fd --- /dev/null +++ b/MdePkg/Library/BaseLib/AArch64/ArmReadCntPctReg.asm @@ -0,0 +1,30 @@ +;------------------------------------------------------------------------------
+;
+; ArmReadCntPctReg() for AArch64
+;
+; Copyright (c) 2023 - 2024, Arm Limited. All rights reserved.<BR>
+;
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+;------------------------------------------------------------------------------
+
+ EXPORT ArmReadCntPctReg
+ AREA BaseLib_LowLevel, CODE, READONLY
+
+;/**
+; Reads the CNTPCT_EL0 Register.
+;
+; @return The contents of the CNTPCT_EL0 register.
+;
+;**/
+;UINT64
+;EFIAPI
+;ArmReadCntPctReg (
+; VOID
+; );
+;
+ArmReadCntPctReg
+ mrs x0, cntpct_el0
+ ret
+
+ END
diff --git a/MdePkg/Library/BaseRngLib/AArch64/ArmReadIdIsar0.S b/MdePkg/Library/BaseLib/AArch64/ArmReadIdAA64Isar0Reg.S index d30b63f..4e61b86 100644 --- a/MdePkg/Library/BaseRngLib/AArch64/ArmReadIdIsar0.S +++ b/MdePkg/Library/BaseLib/AArch64/ArmReadIdAA64Isar0Reg.S @@ -1,6 +1,6 @@ #------------------------------------------------------------------------------
#
-# ArmReadIdIsar0() for AArch64
+# ArmReadIdAA64Isar0Reg() for AArch64
#
# Copyright (c) 2021, NUVIA Inc. All rights reserved.<BR>
#
@@ -10,7 +10,7 @@ .text
.p2align 2
-GCC_ASM_EXPORT(ArmReadIdIsar0)
+GCC_ASM_EXPORT(ArmReadIdAA64Isar0Reg)
#/**
# Reads the ID_AA64ISAR0 Register.
@@ -20,11 +20,11 @@ GCC_ASM_EXPORT(ArmReadIdIsar0) #**/
#UINT64
#EFIAPI
-#ArmReadIdIsar0 (
+#ArmReadIdAA64Isar0Reg (
# VOID
# );
#
-ASM_PFX(ArmReadIdIsar0):
+ASM_PFX(ArmReadIdAA64Isar0Reg):
AARCH64_BTI(c)
- mrs x0, id_aa64isar0_el1 // Read ID_AA64ISAR0 Register
+ mrs x0, id_aa64isar0_el1
ret
diff --git a/MdePkg/Library/BaseRngLib/AArch64/ArmReadIdIsar0.asm b/MdePkg/Library/BaseLib/AArch64/ArmReadIdAA64Isar0Reg.asm index 1d9f9a8..790fb90 100644 --- a/MdePkg/Library/BaseRngLib/AArch64/ArmReadIdIsar0.asm +++ b/MdePkg/Library/BaseLib/AArch64/ArmReadIdAA64Isar0Reg.asm @@ -1,6 +1,6 @@ ;------------------------------------------------------------------------------
;
-; ArmReadIdIsar0() for AArch64
+; ArmReadIdAA64Isar0Reg() for AArch64
;
; Copyright (c) 2021, NUVIA Inc. All rights reserved.<BR>
;
@@ -8,7 +8,7 @@ ;
;------------------------------------------------------------------------------
- EXPORT ArmReadIdIsar0
+ EXPORT ArmReadIdAA64Isar0Reg
AREA BaseLib_LowLevel, CODE, READONLY
;/**
@@ -19,12 +19,12 @@ ;**/
;UINT64
;EFIAPI
-;ArmReadIdIsar0 (
+;ArmReadIdAA64Isar0Reg (
; VOID
; );
;
-ArmReadIdIsar0
- mrs x0, id_aa64isar0_el1 // Read ID_AA64ISAR0 Register
+ArmReadIdAA64Isar0Reg
+ mrs x0, id_aa64isar0_el1
ret
END
diff --git a/MdePkg/Library/BaseLib/BaseLib.inf b/MdePkg/Library/BaseLib/BaseLib.inf index 26e66a8..e3336c5 100644 --- a/MdePkg/Library/BaseLib/BaseLib.inf +++ b/MdePkg/Library/BaseLib/BaseLib.inf @@ -3,7 +3,7 @@ #
# Copyright (c) 2007 - 2021, Intel Corporation. All rights reserved.<BR>
# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
-# Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
+# Portions copyright (c) 2011 - 2024, Arm Limited. All rights reserved.<BR>
# Copyright (c) 2020 - 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -378,6 +378,8 @@ AArch64/SetJumpLongJump.S | GCC
AArch64/CpuBreakpoint.S | GCC
AArch64/SpeculationBarrier.S | GCC
+ AArch64/ArmReadCntPctReg.S | GCC
+ AArch64/ArmReadIdAA64Isar0Reg.S | GCC
AArch64/MemoryFence.asm | MSFT
AArch64/SwitchStack.asm | MSFT
@@ -387,6 +389,8 @@ AArch64/SetJumpLongJump.asm | MSFT
AArch64/CpuBreakpoint.asm | MSFT
AArch64/SpeculationBarrier.asm | MSFT
+ AArch64/ArmReadCntPctReg.asm | MSFT
+ AArch64/ArmReadIdAA64Isar0Reg.asm | MSFT
[Sources.RISCV64]
Math64.c
diff --git a/MdePkg/Library/BaseLib/CheckSum.c b/MdePkg/Library/BaseLib/CheckSum.c index 57d324c..1c82a53 100644 --- a/MdePkg/Library/BaseLib/CheckSum.c +++ b/MdePkg/Library/BaseLib/CheckSum.c @@ -762,3 +762,72 @@ CalculateCrc32c ( return ~Crc;
}
+
+// The lookup table is inherited from [https://crccalc.com/](https://crccalc.com/%60)
+GLOBAL_REMOVE_IF_UNREFERENCED STATIC CONST UINT16 mCrc16CcittFLookupTable[256] = {
+ 0x0000, 0x1021, 0x2042, 0x3063, 0x4084, 0x50a5, 0x60c6, 0x70e7,
+ 0x8108, 0x9129, 0xa14a, 0xb16b, 0xc18c, 0xd1ad, 0xe1ce, 0xf1ef,
+ 0x1231, 0x0210, 0x3273, 0x2252, 0x52b5, 0x4294, 0x72f7, 0x62d6,
+ 0x9339, 0x8318, 0xb37b, 0xa35a, 0xd3bd, 0xc39c, 0xf3ff, 0xe3de,
+ 0x2462, 0x3443, 0x0420, 0x1401, 0x64e6, 0x74c7, 0x44a4, 0x5485,
+ 0xa56a, 0xb54b, 0x8528, 0x9509, 0xe5ee, 0xf5cf, 0xc5ac, 0xd58d,
+ 0x3653, 0x2672, 0x1611, 0x0630, 0x76d7, 0x66f6, 0x5695, 0x46b4,
+ 0xb75b, 0xa77a, 0x9719, 0x8738, 0xf7df, 0xe7fe, 0xd79d, 0xc7bc,
+ 0x48c4, 0x58e5, 0x6886, 0x78a7, 0x0840, 0x1861, 0x2802, 0x3823,
+ 0xc9cc, 0xd9ed, 0xe98e, 0xf9af, 0x8948, 0x9969, 0xa90a, 0xb92b,
+ 0x5af5, 0x4ad4, 0x7ab7, 0x6a96, 0x1a71, 0x0a50, 0x3a33, 0x2a12,
+ 0xdbfd, 0xcbdc, 0xfbbf, 0xeb9e, 0x9b79, 0x8b58, 0xbb3b, 0xab1a,
+ 0x6ca6, 0x7c87, 0x4ce4, 0x5cc5, 0x2c22, 0x3c03, 0x0c60, 0x1c41,
+ 0xedae, 0xfd8f, 0xcdec, 0xddcd, 0xad2a, 0xbd0b, 0x8d68, 0x9d49,
+ 0x7e97, 0x6eb6, 0x5ed5, 0x4ef4, 0x3e13, 0x2e32, 0x1e51, 0x0e70,
+ 0xff9f, 0xefbe, 0xdfdd, 0xcffc, 0xbf1b, 0xaf3a, 0x9f59, 0x8f78,
+ 0x9188, 0x81a9, 0xb1ca, 0xa1eb, 0xd10c, 0xc12d, 0xf14e, 0xe16f,
+ 0x1080, 0x00a1, 0x30c2, 0x20e3, 0x5004, 0x4025, 0x7046, 0x6067,
+ 0x83b9, 0x9398, 0xa3fb, 0xb3da, 0xc33d, 0xd31c, 0xe37f, 0xf35e,
+ 0x02b1, 0x1290, 0x22f3, 0x32d2, 0x4235, 0x5214, 0x6277, 0x7256,
+ 0xb5ea, 0xa5cb, 0x95a8, 0x8589, 0xf56e, 0xe54f, 0xd52c, 0xc50d,
+ 0x34e2, 0x24c3, 0x14a0, 0x0481, 0x7466, 0x6447, 0x5424, 0x4405,
+ 0xa7db, 0xb7fa, 0x8799, 0x97b8, 0xe75f, 0xf77e, 0xc71d, 0xd73c,
+ 0x26d3, 0x36f2, 0x0691, 0x16b0, 0x6657, 0x7676, 0x4615, 0x5634,
+ 0xd94c, 0xc96d, 0xf90e, 0xe92f, 0x99c8, 0x89e9, 0xb98a, 0xa9ab,
+ 0x5844, 0x4865, 0x7806, 0x6827, 0x18c0, 0x08e1, 0x3882, 0x28a3,
+ 0xcb7d, 0xdb5c, 0xeb3f, 0xfb1e, 0x8bf9, 0x9bd8, 0xabbb, 0xbb9a,
+ 0x4a75, 0x5a54, 0x6a37, 0x7a16, 0x0af1, 0x1ad0, 0x2ab3, 0x3a92,
+ 0xfd2e, 0xed0f, 0xdd6c, 0xcd4d, 0xbdaa, 0xad8b, 0x9de8, 0x8dc9,
+ 0x7c26, 0x6c07, 0x5c64, 0x4c45, 0x3ca2, 0x2c83, 0x1ce0, 0x0cc1,
+ 0xef1f, 0xff3e, 0xcf5d, 0xdf7c, 0xaf9b, 0xbfba, 0x8fd9, 0x9ff8,
+ 0x6e17, 0x7e36, 0x4e55, 0x5e74, 0x2e93, 0x3eb2, 0x0ed1, 0x1ef0,
+};
+
+/**
+ Calculates the CRC16-CCITT-FALSE checksum of the given buffer.
+
+ @param[in] Buffer Pointer to the buffer.
+ @param[in] Length Length of the buffer, in bytes.
+ @param[in] InitialValue Initial value of the CRC.
+
+ @return The CRC16-CCITT-FALSE checksum.
+**/
+UINT16
+EFIAPI
+CalculateCrc16CcittF (
+ IN CONST VOID *Buffer,
+ IN UINTN Length,
+ IN UINT16 InitialValue
+ )
+{
+ CONST UINT8 *Buf;
+ UINT16 Crc;
+
+ ASSERT (Buffer != NULL);
+ ASSERT (Length <= (MAX_ADDRESS - ((UINTN)Buffer) + 1));
+
+ Buf = Buffer;
+ Crc = InitialValue;
+
+ while (Length-- != 0) {
+ Crc = mCrc16CcittFLookupTable[((Crc >> 8) ^ *(Buf++)) & 0xFF] ^ (Crc << 8);
+ }
+
+ return Crc;
+}
diff --git a/MdePkg/Library/BaseLib/LoongArch64/AsmCsr.S b/MdePkg/Library/BaseLib/LoongArch64/AsmCsr.S index 3a87941..bb57924 100644 --- a/MdePkg/Library/BaseLib/LoongArch64/AsmCsr.S +++ b/MdePkg/Library/BaseLib/LoongArch64/AsmCsr.S @@ -50,12 +50,12 @@ TlbCsrRd: jirl $zero, $t0, 0
CfgCsrRd:
- li.w $t0, LOONGARCH_CSR_CPUNUM
+ li.w $t0, LOONGARCH_CSR_CPUID
bltu $a0, $t0, ReadSelNumErr
li.w $t0, LOONGARCH_CSR_PRCFG3
bltu $t0, $a0, KcsCsrRd
la.pcrel $t0, CfgCsrRead
- addi.w $t1, $a0, -LOONGARCH_CSR_CPUNUM
+ addi.w $t1, $a0, -LOONGARCH_CSR_CPUID
alsl.d $t0, $t1, $t0, 3
jirl $zero, $t0, 0
@@ -100,8 +100,7 @@ DirMapCsrRd: jirl $zero, $t0, 0
ReadSelNumErr:
- addi.d $a0, $zero, -1
- jirl $zero, $ra, 0
+ break 0
BasicCsrRead:
CsrSel = LOONGARCH_CSR_CRMD
@@ -118,8 +117,8 @@ TlbCsrRead: .endr
CfgCsrRead:
- CsrSel = LOONGARCH_CSR_CPUNUM
- .rept LOONGARCH_CSR_PRCFG3 - LOONGARCH_CSR_CPUNUM + 1
+ CsrSel = LOONGARCH_CSR_CPUID
+ .rept LOONGARCH_CSR_PRCFG3 - LOONGARCH_CSR_CPUID + 1
AsmCsrRd CsrSel
CsrSel = CsrSel + 1
.endr
@@ -175,12 +174,12 @@ TlbCsrWr: jirl $zero, $t0, 0
CfgCsrWr:
- li.w $t0, LOONGARCH_CSR_CPUNUM
+ li.w $t0, LOONGARCH_CSR_CPUID
bltu $a0, $t0, WriteSelNumErr
li.w $t0, LOONGARCH_CSR_PRCFG3
bltu $t0, $a0, KcsCsrWr
la.pcrel $t0, CfgCsrWrite
- addi.w $t1, $a0, -LOONGARCH_CSR_CPUNUM
+ addi.w $t1, $a0, -LOONGARCH_CSR_CPUID
alsl.d $t0, $t1, $t0, 3
move $a0, $a1
jirl $zero, $t0, 0
@@ -230,8 +229,7 @@ DirMapCsrWr: jirl $zero, $t0, 0
WriteSelNumErr:
- addi.d $a0, $zero, -1
- jirl $zero, $ra, 0
+ break 0
BasicCsrWrite:
CsrSel = LOONGARCH_CSR_CRMD
@@ -248,8 +246,8 @@ TlbCsrWrite: .endr
CfgCsrWrite:
- CsrSel = LOONGARCH_CSR_CPUNUM
- .rept LOONGARCH_CSR_PRCFG3 - LOONGARCH_CSR_CPUNUM + 1
+ CsrSel = LOONGARCH_CSR_CPUID
+ .rept LOONGARCH_CSR_PRCFG3 - LOONGARCH_CSR_CPUID + 1
AsmCsrWr CsrSel
CsrSel = CsrSel + 1
.endr
@@ -308,12 +306,12 @@ TlbCsrXchg: jirl $zero, $t0, 0
CfgCsrXchg:
- li.w $t0, LOONGARCH_CSR_CPUNUM
+ li.w $t0, LOONGARCH_CSR_CPUID
bltu $a0, $t0, XchgSelNumErr
li.w $t0, LOONGARCH_CSR_PRCFG3
bltu $t0, $a0, KcsCsrXchg
la.pcrel $t0, CfgCsrXchange
- addi.w $t1, $a0, -LOONGARCH_CSR_CPUNUM
+ addi.w $t1, $a0, -LOONGARCH_CSR_CPUID
alsl.d $t0, $t1, $t0, 3
move $a0, $a1
move $a1, $a2
@@ -368,8 +366,7 @@ DirMapCsrXchg: jirl $zero, $t0, 0
XchgSelNumErr:
- addi.d $a0, $zero, -1
- jirl $zero, $ra, 0
+ break 0
BasicCsrXchange:
CsrSel = LOONGARCH_CSR_CRMD
@@ -386,8 +383,8 @@ TlbCsrXchange: .endr
CfgCsrXchange:
- CsrSel = LOONGARCH_CSR_CPUNUM
- .rept LOONGARCH_CSR_PRCFG3 - LOONGARCH_CSR_CPUNUM + 1
+ CsrSel = LOONGARCH_CSR_CPUID
+ .rept LOONGARCH_CSR_PRCFG3 - LOONGARCH_CSR_CPUID + 1
AsmCsrXChange CsrSel
CsrSel = CsrSel + 1
.endr
diff --git a/MdePkg/Library/BaseLib/LoongArch64/Csr.c b/MdePkg/Library/BaseLib/LoongArch64/Csr.c index f2ec80b..5a40bfe 100644 --- a/MdePkg/Library/BaseLib/LoongArch64/Csr.c +++ b/MdePkg/Library/BaseLib/LoongArch64/Csr.c @@ -29,7 +29,8 @@ AsmCsrXChg ( @param[in] Select CSR read instruction select values.
- @return The return value of csrrd instruction, return -1 means Select is out of support.
+ @return The return value of csrrd instruction,
+ if a break exception is triggered, the Select is out of support.
**/
UINTN
EFIAPI
@@ -47,7 +48,7 @@ CsrRead ( @param[in, out] Value The csrwr will write the value.
@return The return value of csrwr instruction, that is, store the old value of
- the register, return -1 means Select is out of support.
+ the register, if a break exception is triggered, the Select is out of support.
**/
UINTN
EFIAPI
@@ -67,7 +68,7 @@ CsrWrite ( @param[in] Mask The csrxchg mask value.
@return The return value of csrxchg instruction, that is, store the old value of
- the register, return -1 means Select is out of support.
+ the register, if a break exception is triggered, the Select is out of support.
**/
UINTN
EFIAPI
diff --git a/MdePkg/Library/BaseMemoryLibMmx/BaseMemoryLibMmx.inf b/MdePkg/Library/BaseMemoryLibMmx/BaseMemoryLibMmx.inf index c470fa4..18fc587 100644 --- a/MdePkg/Library/BaseMemoryLibMmx/BaseMemoryLibMmx.inf +++ b/MdePkg/Library/BaseMemoryLibMmx/BaseMemoryLibMmx.inf @@ -57,17 +57,6 @@ Ia32/ZeroMem.nasm
Ia32/SetMem.nasm
Ia32/CopyMem.nasm
- Ia32/ScanMem64.nasm
- Ia32/ScanMem32.nasm
- Ia32/ScanMem16.nasm
- Ia32/ScanMem8.nasm
- Ia32/CompareMem.nasm
- Ia32/SetMem64.nasm
- Ia32/SetMem32.nasm
- Ia32/SetMem16.nasm
- Ia32/ZeroMem.nasm
- Ia32/SetMem.nasm
- Ia32/CopyMem.nasm
Ia32/IsZeroBuffer.nasm
[Sources.X64]
@@ -82,20 +71,8 @@ X64/SetMem16.nasm
X64/SetMem.nasm
X64/CopyMem.nasm
- X64/ScanMem64.nasm
- X64/ScanMem32.nasm
- X64/ScanMem16.nasm
- X64/ScanMem8.nasm
- X64/CompareMem.nasm
- X64/SetMem64.nasm
- X64/SetMem32.nasm
- X64/SetMem16.nasm
- X64/ZeroMem.nasm
- X64/SetMem.nasm
- X64/CopyMem.nasm
X64/IsZeroBuffer.nasm
-
[LibraryClasses]
DebugLib
BaseLib
diff --git a/MdePkg/Library/BaseMemoryLibOptDxe/BaseMemoryLibOptDxe.inf b/MdePkg/Library/BaseMemoryLibOptDxe/BaseMemoryLibOptDxe.inf index 366a6c6..6a7fa9a 100644 --- a/MdePkg/Library/BaseMemoryLibOptDxe/BaseMemoryLibOptDxe.inf +++ b/MdePkg/Library/BaseMemoryLibOptDxe/BaseMemoryLibOptDxe.inf @@ -40,17 +40,6 @@ Ia32/SetMem16.nasm
Ia32/SetMem.nasm
Ia32/CopyMem.nasm
- Ia32/ScanMem64.nasm
- Ia32/ScanMem32.nasm
- Ia32/ScanMem16.nasm
- Ia32/ScanMem8.nasm
- Ia32/CompareMem.nasm
- Ia32/ZeroMem.nasm
- Ia32/SetMem64.nasm
- Ia32/SetMem32.nasm
- Ia32/SetMem16.nasm
- Ia32/SetMem.nasm
- Ia32/CopyMem.nasm
Ia32/IsZeroBuffer.nasm
MemLibGuid.c
diff --git a/MdePkg/Library/BaseMemoryLibOptPei/BaseMemoryLibOptPei.inf b/MdePkg/Library/BaseMemoryLibOptPei/BaseMemoryLibOptPei.inf index 0bb4b7c..43c2cc2 100644 --- a/MdePkg/Library/BaseMemoryLibOptPei/BaseMemoryLibOptPei.inf +++ b/MdePkg/Library/BaseMemoryLibOptPei/BaseMemoryLibOptPei.inf @@ -27,6 +27,19 @@ [Sources]
MemLibInternals.h
+ ScanMem64Wrapper.c
+ ScanMem32Wrapper.c
+ ScanMem16Wrapper.c
+ ScanMem8Wrapper.c
+ ZeroMemWrapper.c
+ CompareMemWrapper.c
+ SetMem64Wrapper.c
+ SetMem32Wrapper.c
+ SetMem16Wrapper.c
+ SetMemWrapper.c
+ CopyMemWrapper.c
+ IsZeroBufferWrapper.c
+ MemLibGuid.c
[Sources.Ia32]
Ia32/ScanMem64.nasm
@@ -40,31 +53,7 @@ Ia32/SetMem16.nasm
Ia32/SetMem.nasm
Ia32/CopyMem.nasm
- Ia32/ScanMem64.nasm
- Ia32/ScanMem32.nasm
- Ia32/ScanMem16.nasm
- Ia32/ScanMem8.nasm
- Ia32/CompareMem.nasm
- Ia32/ZeroMem.nasm
- Ia32/SetMem64.nasm
- Ia32/SetMem32.nasm
- Ia32/SetMem16.nasm
- Ia32/SetMem.nasm
- Ia32/CopyMem.nasm
Ia32/IsZeroBuffer.nasm
- ScanMem64Wrapper.c
- ScanMem32Wrapper.c
- ScanMem16Wrapper.c
- ScanMem8Wrapper.c
- ZeroMemWrapper.c
- CompareMemWrapper.c
- SetMem64Wrapper.c
- SetMem32Wrapper.c
- SetMem16Wrapper.c
- SetMemWrapper.c
- CopyMemWrapper.c
- IsZeroBufferWrapper.c
- MemLibGuid.c
[Sources.X64]
X64/ScanMem64.nasm
@@ -79,20 +68,6 @@ X64/SetMem.nasm
X64/CopyMem.nasm
X64/IsZeroBuffer.nasm
- ScanMem64Wrapper.c
- ScanMem32Wrapper.c
- ScanMem16Wrapper.c
- ScanMem8Wrapper.c
- ZeroMemWrapper.c
- CompareMemWrapper.c
- SetMem64Wrapper.c
- SetMem32Wrapper.c
- SetMem16Wrapper.c
- SetMemWrapper.c
- CopyMemWrapper.c
- IsZeroBufferWrapper.c
- MemLibGuid.c
-
[Packages]
MdePkg/MdePkg.dec
diff --git a/MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf b/MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf index 9d4f876..59983d0 100644 --- a/MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +++ b/MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf @@ -53,17 +53,6 @@ Ia32/SetMem16.nasm
Ia32/SetMem.nasm
Ia32/CopyMem.nasm
- Ia32/ScanMem64.nasm
- Ia32/ScanMem32.nasm
- Ia32/ScanMem16.nasm
- Ia32/ScanMem8.nasm
- Ia32/CompareMem.nasm
- Ia32/ZeroMem.nasm
- Ia32/SetMem64.nasm
- Ia32/SetMem32.nasm
- Ia32/SetMem16.nasm
- Ia32/SetMem.nasm
- Ia32/CopyMem.nasm
Ia32/IsZeroBuffer.nasm
[Sources.X64]
@@ -78,17 +67,6 @@ X64/SetMem16.nasm
X64/SetMem.nasm
X64/CopyMem.nasm
- X64/ScanMem64.nasm
- X64/ScanMem32.nasm
- X64/ScanMem16.nasm
- X64/ScanMem8.nasm
- X64/CompareMem.nasm
- X64/ZeroMem.nasm
- X64/SetMem64.nasm
- X64/SetMem32.nasm
- X64/SetMem16.nasm
- X64/SetMem.nasm
- X64/CopyMem.nasm
X64/IsZeroBuffer.nasm
[Packages]
diff --git a/MdePkg/Library/BaseMemoryLibSse2/BaseMemoryLibSse2.inf b/MdePkg/Library/BaseMemoryLibSse2/BaseMemoryLibSse2.inf index 79618c9..69a29a1 100644 --- a/MdePkg/Library/BaseMemoryLibSse2/BaseMemoryLibSse2.inf +++ b/MdePkg/Library/BaseMemoryLibSse2/BaseMemoryLibSse2.inf @@ -52,17 +52,6 @@ Ia32/SetMem16.nasm
Ia32/SetMem.nasm
Ia32/CopyMem.nasm
- Ia32/ScanMem64.nasm
- Ia32/ScanMem32.nasm
- Ia32/ScanMem16.nasm
- Ia32/ScanMem8.nasm
- Ia32/CompareMem.nasm
- Ia32/ZeroMem.nasm
- Ia32/SetMem64.nasm
- Ia32/SetMem32.nasm
- Ia32/SetMem16.nasm
- Ia32/SetMem.nasm
- Ia32/CopyMem.nasm
Ia32/IsZeroBuffer.nasm
[Sources.X64]
@@ -77,17 +66,6 @@ X64/SetMem16.nasm
X64/SetMem.nasm
X64/CopyMem.nasm
- X64/ScanMem64.nasm
- X64/ScanMem32.nasm
- X64/ScanMem16.nasm
- X64/ScanMem8.nasm
- X64/CompareMem.nasm
- X64/ZeroMem.nasm
- X64/SetMem64.nasm
- X64/SetMem32.nasm
- X64/SetMem16.nasm
- X64/SetMem.nasm
- X64/CopyMem.nasm
X64/IsZeroBuffer.nasm
[Packages]
diff --git a/MdePkg/Library/BaseRngLib/AArch64/ArmRng.h b/MdePkg/Library/BaseRngLib/AArch64/ArmRng.h index 2d6ef48..b4b3c97 100644 --- a/MdePkg/Library/BaseRngLib/AArch64/ArmRng.h +++ b/MdePkg/Library/BaseRngLib/AArch64/ArmRng.h @@ -27,16 +27,4 @@ ArmRndr ( OUT UINT64 *Rand
);
-/**
- Reads the ID_AA64ISAR0 Register.
-
- @return The contents of the ID_AA64ISAR0 register.
-
-**/
-UINT64
-EFIAPI
-ArmReadIdIsar0 (
- VOID
- );
-
#endif /* ARM_RNG_H_ */
diff --git a/MdePkg/Library/BaseRngLib/AArch64/Rndr.c b/MdePkg/Library/BaseRngLib/AArch64/Rndr.c index 3a556a2..2c53443 100644 --- a/MdePkg/Library/BaseRngLib/AArch64/Rndr.c +++ b/MdePkg/Library/BaseRngLib/AArch64/Rndr.c @@ -21,11 +21,6 @@ STATIC BOOLEAN mRndrSupported;
-//
-// Bit mask used to determine if RNDR instruction is supported.
-//
-#define RNDR_MASK ((UINT64)MAX_UINT16 << 60U)
-
/**
The constructor function checks whether or not RNDR instruction is supported
by the host hardware.
@@ -49,9 +44,8 @@ BaseRngLibConstructor ( // Determine RNDR support by examining bits 63:60 of the ISAR0 register returned by
// MSR. A non-zero value indicates that the processor supports the RNDR instruction.
//
- Isar0 = ArmReadIdIsar0 ();
-
- mRndrSupported = ((Isar0 & RNDR_MASK) != 0);
+ Isar0 = ArmReadIdAA64Isar0Reg ();
+ mRndrSupported = !!((Isar0 >> ARM_ID_AA64ISAR0_EL1_RNDR_SHIFT) & ARM_ID_AA64ISAR0_EL1_RNDR_MASK);
return EFI_SUCCESS;
}
diff --git a/MdePkg/Library/BaseRngLib/BaseRngLib.inf b/MdePkg/Library/BaseRngLib/BaseRngLib.inf index 49503b1..53833a7 100644 --- a/MdePkg/Library/BaseRngLib/BaseRngLib.inf +++ b/MdePkg/Library/BaseRngLib/BaseRngLib.inf @@ -38,10 +38,8 @@ AArch64/Rndr.c
AArch64/ArmRng.h
- AArch64/ArmReadIdIsar0.S | GCC
AArch64/ArmRng.S | GCC
- AArch64/ArmReadIdIsar0.asm | MSFT
AArch64/ArmRng.asm | MSFT
[Guids.AARCH64]
@@ -50,6 +48,10 @@ [Guids.Ia32, Guids.X64]
gEfiRngAlgorithmSp80090Ctr256Guid
+[Sources.RISCV64]
+ Riscv/Rng.c
+ Riscv/Seed.S | GCC
+
[Packages]
MdePkg/MdePkg.dec
@@ -59,3 +61,7 @@ [LibraryClasses]
BaseLib
DebugLib
+
+[Pcd.RISCV64]
+ # Does the CPU support the Zkr extension (for the `Seed` CSR)
+ gEfiMdePkgTokenSpaceGuid.PcdRiscVFeatureOverride ## CONSUMES
diff --git a/MdePkg/Library/BaseRngLib/Riscv/Rng.c b/MdePkg/Library/BaseRngLib/Riscv/Rng.c new file mode 100644 index 0000000..305ab60 --- /dev/null +++ b/MdePkg/Library/BaseRngLib/Riscv/Rng.c @@ -0,0 +1,277 @@ +/** @file
+ Random number generator service that uses the SEED instruction
+ to provide pseudorandom numbers.
+
+ Copyright (c) 2024, Rivos, Inc.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+ **/
+
+#include <Uefi.h>
+#include <Library/BaseLib.h>
+#include <Library/DebugLib.h>
+#include <Library/RngLib.h>
+#include <Register/RiscV64/RiscVEncoding.h>
+
+#include "BaseRngLibInternals.h"
+#define RISCV_CPU_FEATURE_ZKR_BITMASK 0x8
+
+#define SEED_RETRY_LOOPS 100
+
+// 64-bit Mersenne Twister implementation
+// A widely used pseudo random number generator. It performs bit shifts etc to
+// achieve the random number. It's output is determined by SEED value generated
+// by RISC-V SEED CSR"
+
+#define STATE_SIZE 312
+#define MIDDLE 156
+#define INIT_SHIFT 62
+#define TWIST_MASK 0xb5026f5aa96619e9ULL
+#define INIT_FACT 6364136223846793005ULL
+#define SHIFT1 29
+#define MASK1 0x5555555555555555ULL
+#define SHIFT2 17
+#define MASK2 0x71d67fffeda60000ULL
+#define SHIFT3 37
+#define MASK3 0xfff7eee000000000ULL
+#define SHIFT4 43
+
+#define LOWER_MASK 0x7fffffff
+#define UPPER_MASK (~(UINT64)LOWER_MASK)
+
+static UINT64 mState[STATE_SIZE];
+static UINTN mIndex = STATE_SIZE + 1;
+
+/**
+ Initialize mState to defualt state.
+
+ @param[in] S Input seed value
+ **/
+STATIC
+VOID
+SeedRng (
+ IN UINT64 S
+ )
+{
+ UINTN I;
+
+ mIndex = STATE_SIZE;
+ mState[0] = S;
+
+ for (I = 1; I < STATE_SIZE; I++) {
+ mState[I] = (INIT_FACT * (mState[I - 1] ^ (mState[I - 1] >> INIT_SHIFT))) + I;
+ }
+}
+
+/**
+ Initializes mState with entropy values. The initialization is based on the
+ Seed value populated in mState[0] which then influences all the other values
+ in the mState array. Later values are retrieved from the same array instead
+ of calling trng instruction every time.
+
+ **/
+STATIC
+VOID
+TwistRng (
+ VOID
+ )
+{
+ UINTN I;
+ UINT64 X;
+
+ for (I = 0; I < STATE_SIZE; I++) {
+ X = (mState[I] & UPPER_MASK) | (mState[(I + 1) % STATE_SIZE] & LOWER_MASK);
+ X = (X >> 1) ^ (X & 1 ? TWIST_MASK : 0);
+ mState[I] = mState[(I + MIDDLE) % STATE_SIZE] ^ X;
+ }
+
+ mIndex = 0;
+}
+
+// Defined in Seed.S
+extern UINT64
+ReadSeed (
+ VOID
+ );
+
+/**
+ Gets seed value by executing trng instruction (CSR 0x15) amd returns
+ the see to the caller 64bit value.
+
+ @param[out] Out Buffer pointer to store the 64-bit random value.
+ @retval TRUE Random number generated successfully.
+ @retval FALSE Failed to generate the random number.
+ **/
+STATIC
+BOOLEAN
+Get64BitSeed (
+ OUT UINT64 *Out
+ )
+{
+ UINT64 Seed;
+ UINTN Retry;
+ UINTN ValidSeeds;
+ UINTN NeededSeeds;
+ UINT16 *Entropy;
+
+ Retry = SEED_RETRY_LOOPS;
+ Entropy = (UINT16 *)Out;
+ NeededSeeds = sizeof (UINT64) / sizeof (UINT16);
+ ValidSeeds = 0;
+
+ if (!ArchIsRngSupported ()) {
+ DEBUG ((DEBUG_ERROR, "Get64BitSeed: HW not supported!\n"));
+ return FALSE;
+ }
+
+ do {
+ Seed = ReadSeed ();
+
+ switch (Seed & SEED_OPST_MASK) {
+ case SEED_OPST_ES16:
+ Entropy[ValidSeeds++] = Seed & SEED_ENTROPY_MASK;
+ if (ValidSeeds == NeededSeeds) {
+ return TRUE;
+ }
+
+ break;
+
+ case SEED_OPST_DEAD:
+ DEBUG ((DEBUG_ERROR, "Get64BitSeed: Unrecoverable error!\n"));
+ return FALSE;
+
+ case SEED_OPST_BIST: // fallthrough
+ case SEED_OPST_WAIT: // fallthrough
+ default:
+ continue;
+ }
+ } while (--Retry);
+
+ return FALSE;
+}
+
+/**
+ Constructor library which initializes Seeds and mStatus array.
+
+ @retval EFI_SUCCESS Intialization was successful.
+ @retval EFI_UNSUPPORTED Feature not supported.
+
+ **/
+EFI_STATUS
+EFIAPI
+BaseRngLibConstructor (
+ VOID
+ )
+{
+ UINT64 Seed;
+
+ if (Get64BitSeed (&Seed)) {
+ SeedRng (Seed);
+ return EFI_SUCCESS;
+ } else {
+ return EFI_UNSUPPORTED;
+ }
+}
+
+/**
+ Generates a 16-bit random number.
+
+ @param[out] Rand Buffer pointer to store the 16-bit random value.
+
+ @retval TRUE Random number generated successfully.
+ @retval FALSE Failed to generate the random number.
+
+ **/
+BOOLEAN
+EFIAPI
+ArchGetRandomNumber16 (
+ OUT UINT16 *Rand
+ )
+{
+ UINT64 Rand64;
+
+ if (ArchGetRandomNumber64 (&Rand64)) {
+ *Rand = Rand64 & MAX_UINT16;
+ return TRUE;
+ }
+
+ return FALSE;
+}
+
+/**
+ Generates a 32-bit random number.
+
+ @param[out] Rand Buffer pointer to store the 32-bit random value.
+
+ @retval TRUE Random number generated successfully.
+ @retval FALSE Failed to generate the random number.
+
+ **/
+BOOLEAN
+EFIAPI
+ArchGetRandomNumber32 (
+ OUT UINT32 *Rand
+ )
+{
+ UINT64 Rand64;
+
+ if (ArchGetRandomNumber64 (&Rand64)) {
+ *Rand = Rand64 & MAX_UINT32;
+ return TRUE;
+ }
+
+ return FALSE;
+}
+
+/**
+ Generates a 64-bit random number.
+
+ @param[out] Rand Buffer pointer to store the 64-bit random value.
+
+ @retval TRUE Random number generated successfully.
+ @retval FALSE Failed to generate the random number.
+
+ **/
+BOOLEAN
+EFIAPI
+ArchGetRandomNumber64 (
+ OUT UINT64 *Rand
+ )
+{
+ UINT64 Y;
+
+ // Never initialized.
+ if (mIndex > STATE_SIZE) {
+ return FALSE;
+ }
+
+ // Mersenne Twister
+ if (mIndex == STATE_SIZE) {
+ TwistRng ();
+ }
+
+ Y = mState[mIndex];
+ Y ^= (Y >> SHIFT1) & MASK1;
+ Y ^= (Y << SHIFT2) & MASK2;
+ Y ^= (Y << SHIFT3) & MASK3;
+ Y ^= Y >> SHIFT4;
+
+ mIndex++;
+
+ *Rand = Y;
+ return TRUE;
+}
+
+/**
+ Checks whether SEED is supported.
+
+ @retval TRUE SEED is supported.
+ **/
+BOOLEAN
+EFIAPI
+ArchIsRngSupported (
+ VOID
+ )
+{
+ return ((PcdGet64 (PcdRiscVFeatureOverride) & RISCV_CPU_FEATURE_ZKR_BITMASK) != 0);
+}
diff --git a/MdePkg/Library/BaseRngLib/Riscv/Seed.S b/MdePkg/Library/BaseRngLib/Riscv/Seed.S new file mode 100644 index 0000000..0028923 --- /dev/null +++ b/MdePkg/Library/BaseRngLib/Riscv/Seed.S @@ -0,0 +1,19 @@ +//------------------------------------------------------------------------------
+//
+// RISC-V cache operation.
+//
+// Copyright (c) 2024, Rivos Inc. All rights reserved.<BR>
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+//------------------------------------------------------------------------------
+
+#include <Register/RiscV64/RiscVImpl.h>
+
+.text
+ .p2align 4
+
+ASM_FUNC (ReadSeed)
+#The SEED CSR must only be accessed with read-write instructions
+csrrw a0, CSR_SEED, x0
+ret
diff --git a/MdePkg/Library/UefiDebugLibDebugPortProtocol/DebugLib.c b/MdePkg/Library/UefiDebugLibDebugPortProtocol/DebugLib.c index c25199b..3314d3f 100644 --- a/MdePkg/Library/UefiDebugLibDebugPortProtocol/DebugLib.c +++ b/MdePkg/Library/UefiDebugLibDebugPortProtocol/DebugLib.c @@ -233,8 +233,8 @@ DebugBPrint ( Print a message of the form "ASSERT <FileName>(<LineNumber>): <Description>\n"
to the debug output device. If DEBUG_PROPERTY_ASSERT_BREAKPOINT_ENABLED bit of
- PcdDebugProperyMask is set then CpuBreakpoint() is called. Otherwise, if
- DEBUG_PROPERTY_ASSERT_DEADLOOP_ENABLED bit of PcdDebugProperyMask is set then
+ PcdDebugPropertyMask is set then CpuBreakpoint() is called. Otherwise, if
+ DEBUG_PROPERTY_ASSERT_DEADLOOP_ENABLED bit of PcdDebugPropertyMask is set then
CpuDeadLoop() is called. If neither of these bits are set, then this function
returns immediately after the message is printed to the debug output device.
DebugAssert() must actively prevent recursion. If DebugAssert() is called while
@@ -327,10 +327,10 @@ DebugClearMemory ( Returns TRUE if ASSERT() macros are enabled.
This function returns TRUE if the DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED bit of
- PcdDebugProperyMask is set. Otherwise FALSE is returned.
+ PcdDebugPropertyMask is set. Otherwise FALSE is returned.
- @retval TRUE The DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED bit of PcdDebugProperyMask is set.
- @retval FALSE The DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED bit of PcdDebugProperyMask is clear.
+ @retval TRUE The DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED bit of PcdDebugPropertyMask is set.
+ @retval FALSE The DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED bit of PcdDebugPropertyMask is clear.
**/
BOOLEAN
@@ -346,10 +346,10 @@ DebugAssertEnabled ( Returns TRUE if DEBUG() macros are enabled.
This function returns TRUE if the DEBUG_PROPERTY_DEBUG_PRINT_ENABLED bit of
- PcdDebugProperyMask is set. Otherwise FALSE is returned.
+ PcdDebugPropertyMask is set. Otherwise FALSE is returned.
- @retval TRUE The DEBUG_PROPERTY_DEBUG_PRINT_ENABLED bit of PcdDebugProperyMask is set.
- @retval FALSE The DEBUG_PROPERTY_DEBUG_PRINT_ENABLED bit of PcdDebugProperyMask is clear.
+ @retval TRUE The DEBUG_PROPERTY_DEBUG_PRINT_ENABLED bit of PcdDebugPropertyMask is set.
+ @retval FALSE The DEBUG_PROPERTY_DEBUG_PRINT_ENABLED bit of PcdDebugPropertyMask is clear.
**/
BOOLEAN
@@ -365,10 +365,10 @@ DebugPrintEnabled ( Returns TRUE if DEBUG_CODE() macros are enabled.
This function returns TRUE if the DEBUG_PROPERTY_DEBUG_CODE_ENABLED bit of
- PcdDebugProperyMask is set. Otherwise FALSE is returned.
+ PcdDebugPropertyMask is set. Otherwise FALSE is returned.
- @retval TRUE The DEBUG_PROPERTY_DEBUG_CODE_ENABLED bit of PcdDebugProperyMask is set.
- @retval FALSE The DEBUG_PROPERTY_DEBUG_CODE_ENABLED bit of PcdDebugProperyMask is clear.
+ @retval TRUE The DEBUG_PROPERTY_DEBUG_CODE_ENABLED bit of PcdDebugPropertyMask is set.
+ @retval FALSE The DEBUG_PROPERTY_DEBUG_CODE_ENABLED bit of PcdDebugPropertyMask is clear.
**/
BOOLEAN
@@ -384,10 +384,10 @@ DebugCodeEnabled ( Returns TRUE if DEBUG_CLEAR_MEMORY() macro is enabled.
This function returns TRUE if the DEBUG_PROPERTY_CLEAR_MEMORY_ENABLED bit of
- PcdDebugProperyMask is set. Otherwise FALSE is returned.
+ PcdDebugPropertyMask is set. Otherwise FALSE is returned.
- @retval TRUE The DEBUG_PROPERTY_CLEAR_MEMORY_ENABLED bit of PcdDebugProperyMask is set.
- @retval FALSE The DEBUG_PROPERTY_CLEAR_MEMORY_ENABLED bit of PcdDebugProperyMask is clear.
+ @retval TRUE The DEBUG_PROPERTY_CLEAR_MEMORY_ENABLED bit of PcdDebugPropertyMask is set.
+ @retval FALSE The DEBUG_PROPERTY_CLEAR_MEMORY_ENABLED bit of PcdDebugPropertyMask is clear.
**/
BOOLEAN
diff --git a/MdePkg/Library/UefiDebugLibDebugPortProtocol/DebugLibConstructor.c b/MdePkg/Library/UefiDebugLibDebugPortProtocol/DebugLibConstructor.c index 298d17c..0215c27 100644 --- a/MdePkg/Library/UefiDebugLibDebugPortProtocol/DebugLibConstructor.c +++ b/MdePkg/Library/UefiDebugLibDebugPortProtocol/DebugLibConstructor.c @@ -13,7 +13,7 @@ #include <Library/BaseMemoryLib.h>
//
-// BOOLEAN value to indicate if it is at the post ExitBootServices pahse
+// BOOLEAN value to indicate if it is at the post ExitBootServices phase
//
BOOLEAN mPostEBS = FALSE;
@@ -34,9 +34,10 @@ EFI_BOOT_SERVICES *mDebugBS; @param Context Pointer to the notification function's context.
**/
+static
VOID
EFIAPI
-ExitBootServicesCallback (
+UefiDebugLibDebugPortProtocolExitBootServicesCallback (
EFI_EVENT Event,
VOID *Context
)
@@ -67,7 +68,7 @@ DxeDebugLibConstructor ( mDebugBS->CreateEvent (
EVT_SIGNAL_EXIT_BOOT_SERVICES,
TPL_NOTIFY,
- ExitBootServicesCallback,
+ UefiDebugLibDebugPortProtocolExitBootServicesCallback,
NULL,
&mExitBootServicesEvent
);
diff --git a/MdePkg/Library/UefiDebugLibStdErr/DebugLib.c b/MdePkg/Library/UefiDebugLibStdErr/DebugLib.c index 5b28cd1..dc9c525 100644 --- a/MdePkg/Library/UefiDebugLibStdErr/DebugLib.c +++ b/MdePkg/Library/UefiDebugLibStdErr/DebugLib.c @@ -177,8 +177,8 @@ DebugBPrint ( Print a message of the form "ASSERT <FileName>(<LineNumber>): <Description>\n"
to the debug output device. If DEBUG_PROPERTY_ASSERT_BREAKPOINT_ENABLED bit of
- PcdDebugProperyMask is set then CpuBreakpoint() is called. Otherwise, if
- DEBUG_PROPERTY_ASSERT_DEADLOOP_ENABLED bit of PcdDebugProperyMask is set then
+ PcdDebugPropertyMask is set then CpuBreakpoint() is called. Otherwise, if
+ DEBUG_PROPERTY_ASSERT_DEADLOOP_ENABLED bit of PcdDebugPropertyMask is set then
CpuDeadLoop() is called. If neither of these bits are set, then this function
returns immediately after the message is printed to the debug output device.
DebugAssert() must actively prevent recursion. If DebugAssert() is called while
@@ -273,10 +273,10 @@ DebugClearMemory ( Returns TRUE if ASSERT() macros are enabled.
This function returns TRUE if the DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED bit of
- PcdDebugProperyMask is set. Otherwise FALSE is returned.
+ PcdDebugPropertyMask is set. Otherwise FALSE is returned.
- @retval TRUE The DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED bit of PcdDebugProperyMask is set.
- @retval FALSE The DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED bit of PcdDebugProperyMask is clear.
+ @retval TRUE The DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED bit of PcdDebugPropertyMask is set.
+ @retval FALSE The DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED bit of PcdDebugPropertyMask is clear.
**/
BOOLEAN
@@ -292,10 +292,10 @@ DebugAssertEnabled ( Returns TRUE if DEBUG() macros are enabled.
This function returns TRUE if the DEBUG_PROPERTY_DEBUG_PRINT_ENABLED bit of
- PcdDebugProperyMask is set. Otherwise FALSE is returned.
+ PcdDebugPropertyMask is set. Otherwise FALSE is returned.
- @retval TRUE The DEBUG_PROPERTY_DEBUG_PRINT_ENABLED bit of PcdDebugProperyMask is set.
- @retval FALSE The DEBUG_PROPERTY_DEBUG_PRINT_ENABLED bit of PcdDebugProperyMask is clear.
+ @retval TRUE The DEBUG_PROPERTY_DEBUG_PRINT_ENABLED bit of PcdDebugPropertyMask is set.
+ @retval FALSE The DEBUG_PROPERTY_DEBUG_PRINT_ENABLED bit of PcdDebugPropertyMask is clear.
**/
BOOLEAN
@@ -311,10 +311,10 @@ DebugPrintEnabled ( Returns TRUE if DEBUG_CODE() macros are enabled.
This function returns TRUE if the DEBUG_PROPERTY_DEBUG_CODE_ENABLED bit of
- PcdDebugProperyMask is set. Otherwise FALSE is returned.
+ PcdDebugPropertyMask is set. Otherwise FALSE is returned.
- @retval TRUE The DEBUG_PROPERTY_DEBUG_CODE_ENABLED bit of PcdDebugProperyMask is set.
- @retval FALSE The DEBUG_PROPERTY_DEBUG_CODE_ENABLED bit of PcdDebugProperyMask is clear.
+ @retval TRUE The DEBUG_PROPERTY_DEBUG_CODE_ENABLED bit of PcdDebugPropertyMask is set.
+ @retval FALSE The DEBUG_PROPERTY_DEBUG_CODE_ENABLED bit of PcdDebugPropertyMask is clear.
**/
BOOLEAN
@@ -330,10 +330,10 @@ DebugCodeEnabled ( Returns TRUE if DEBUG_CLEAR_MEMORY() macro is enabled.
This function returns TRUE if the DEBUG_PROPERTY_CLEAR_MEMORY_ENABLED bit of
- PcdDebugProperyMask is set. Otherwise FALSE is returned.
+ PcdDebugPropertyMask is set. Otherwise FALSE is returned.
- @retval TRUE The DEBUG_PROPERTY_CLEAR_MEMORY_ENABLED bit of PcdDebugProperyMask is set.
- @retval FALSE The DEBUG_PROPERTY_CLEAR_MEMORY_ENABLED bit of PcdDebugProperyMask is clear.
+ @retval TRUE The DEBUG_PROPERTY_CLEAR_MEMORY_ENABLED bit of PcdDebugPropertyMask is set.
+ @retval FALSE The DEBUG_PROPERTY_CLEAR_MEMORY_ENABLED bit of PcdDebugPropertyMask is clear.
**/
BOOLEAN
diff --git a/MdePkg/Library/UefiDevicePathLib/DevicePathFromText.c b/MdePkg/Library/UefiDevicePathLib/DevicePathFromText.c index 1aaa968..86ecb66 100644 --- a/MdePkg/Library/UefiDevicePathLib/DevicePathFromText.c +++ b/MdePkg/Library/UefiDevicePathLib/DevicePathFromText.c @@ -922,8 +922,8 @@ DevPathFromTextAcpiExp ( AcpiEx->HID = EisaIdFromText (HIDStr);
//
- // According to UEFI spec, the CID parametr is optional and has a default value of 0.
- // So when the CID parametr is not specified or specified as 0 in the text device node.
+ // According to UEFI spec, the CID parameter is optional and has a default value of 0.
+ // So when the CID parameter is not specified or specified as 0 in the text device node.
// Set the CID to 0 in the ACPI extension device path structure.
//
if ((*CIDStr == L'\0') || (*CIDStr == L'0')) {
diff --git a/MdePkg/Library/UefiDevicePathLib/DevicePathToText.c b/MdePkg/Library/UefiDevicePathLib/DevicePathToText.c index 468baa5..afbd590 100644 --- a/MdePkg/Library/UefiDevicePathLib/DevicePathToText.c +++ b/MdePkg/Library/UefiDevicePathLib/DevicePathToText.c @@ -1003,8 +1003,9 @@ DevPathToTextUsbWWID ( //
// In case no NULL terminator in SerialNumber, create a new one with NULL terminator
//
- NewStr = AllocateCopyPool ((Length + 1) * sizeof (CHAR16), SerialNumberStr);
+ NewStr = AllocatePool ((Length + 1) * sizeof (CHAR16));
ASSERT (NewStr != NULL);
+ CopyMem (NewStr, SerialNumberStr, Length * sizeof (CHAR16));
NewStr[Length] = 0;
SerialNumberStr = NewStr;
}
diff --git a/MdePkg/MdeLibs.dsc.inc b/MdePkg/MdeLibs.dsc.inc index ddd2711..a8c8f4e 100644 --- a/MdePkg/MdeLibs.dsc.inc +++ b/MdePkg/MdeLibs.dsc.inc @@ -12,6 +12,7 @@ ##
[LibraryClasses]
+ OrderedCollectionLib|MdePkg/Library/BaseOrderedCollectionRedBlackTreeLib/BaseOrderedCollectionRedBlackTreeLib.inf
ArmTrngLib|MdePkg/Library/BaseArmTrngLibNull/BaseArmTrngLibNull.inf
RegisterFilterLib|MdePkg/Library/RegisterFilterLibNull/RegisterFilterLibNull.inf
CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
diff --git a/MdePkg/MdePkg.dec b/MdePkg/MdePkg.dec index 94170ff..d36bd2e 100644 --- a/MdePkg/MdePkg.dec +++ b/MdePkg/MdePkg.dec @@ -751,6 +751,16 @@ ## Include/Guid/DeviceAuthentication.h
gEfiDeviceSignatureDatabaseGuid = { 0xb9c2b4f4, 0xbf5f, 0x462d, {0x8a, 0xdf, 0xc5, 0xc7, 0xa, 0xc3, 0x5d, 0xad }}
+ ## Include/Guid/ConformanceProfiles.h
+ gEfiConfProfilesTableGuid = { 0x36122546, 0xf7e7, 0x4c8f, { 0xbd, 0x9b, 0xeb, 0x85, 0x25, 0xb5, 0x0c, 0x0b }}
+ gEfiConfProfilesUefiSpecGuid = { 0x523c91af, 0xa195, 0x4382, { 0x81, 0x8d, 0x29, 0x5f, 0xe4, 0x00, 0x64, 0x65 }}
+
+ # GUIDs defined in EBBR
+ #
+ ## Include/Guid/ConformanceProfiles.h
+ gEfiConfProfilesEbbrSpec21Guid = { 0xcce33c35, 0x74ac, 0x4087, { 0xbc, 0xe7, 0x8b, 0x29, 0xb0, 0x2e, 0xeb, 0x27 }}
+ gEfiConfProfilesEbbrSpec22Guid = { 0x9073eed4, 0xe50d, 0x11ee, { 0xb8, 0xb0, 0x8b, 0x68, 0xda, 0x62, 0xfc, 0x80 }}
+
#
# GUID defined in PI1.0
#
@@ -1375,6 +1385,10 @@ ## Include/Protocol/MmCommunication.h
gEfiMmCommunicationProtocolGuid = { 0xc68ed8e2, 0x9dc6, 0x4cbd, { 0x9d, 0x94, 0xdb, 0x65, 0xac, 0xc5, 0xc3, 0x32 }}
+ ## This protocol is a MM protocol published by a standalone MM Foundation code if MM Foundation is loaded in PEI phase.
+ ## This protocol should be installed immediately after DXE IPL installs EFI_PEI_END_OF_PEI_PHASE_PPI
+ gEfiMmEndOfPeiProtocol = { 0xf33e1bf3, 0x980b, 0x4bfb, { 0xa2, 0x9a, 0xb2, 0x9c, 0x86, 0x45, 0x37, 0x32 }}
+
#
# Protocols defined in PI 1.6.
#
@@ -2420,6 +2434,8 @@ # previous stage has feature enabled and user wants to disable it.
# BIT 2 = Page-Based Memory Types (Pbmt). This bit is relevant only if
# previous stage has feature enabled and user wants to disable it.
+ # BIT 3 = Zkr extension.This bit is relevant only if
+ # previous stage has feature enabled and user wants to disable it.
#
gEfiMdePkgTokenSpaceGuid.PcdRiscVFeatureOverride|0xFFFFFFFFFFFFFFFF|UINT64|0x69
diff --git a/MdePkg/Test/UnitTest/Library/BaseLib/Base64UnitTest.c b/MdePkg/Test/UnitTest/Library/BaseLib/Base64UnitTest.c index 9f2d2bd..80d2c9c 100644 --- a/MdePkg/Test/UnitTest/Library/BaseLib/Base64UnitTest.c +++ b/MdePkg/Test/UnitTest/Library/BaseLib/Base64UnitTest.c @@ -390,7 +390,7 @@ SafeStringContraintCheckTest ( }
/**
- Initialze the unit test framework, suite, and unit tests for the
+ Initialize the unit test framework, suite, and unit tests for the
Base64 conversion APIs of BaseLib and run the unit tests.
@retval EFI_SUCCESS All test cases were dispatched.
|