UefiCpuPkg/PiSmmCpuDxeSmm: Clear CR0.WP before modify page table

Clear CR0.WP before modify smm page table. Currently, there is
an assumption that smm pagetable is always RW before ReadyToLock.
However, when AMD SEV is enabled, FvbServicesSmm driver calls
MemEncryptSevClearMmioPageEncMask to clear AddressEncMask bit
in smm page table for this range:
[PcdOvmfFdBaseAddress,PcdOvmfFdBaseAddress+PcdOvmfFirmwareFdSize]
If page slpit happens in this process, new memory for smm page
table is allocated. Then the newly allocated page table memory
is marked as RO in smm page table in this FvbServicesSmm driver,
which may lead to PF if smm code doesn't clear CR0.WP before
modify smm page table when ReadyToLock.

Signed-off-by: Dun Tan <dun.tan@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>

1 files changed, 5 insertions, 0 deletions

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c
index ed6e580..8736b52 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c
@@ -574,6 +574,8 @@ InitPaging (
   BOOLEAN   Nx;

   IA32_CR4  Cr4;

   BOOLEAN   Enable5LevelPaging;

+  BOOLEAN   WpEnabled;

+  BOOLEAN   CetEnabled;

 

   PERF_FUNCTION_BEGIN ();

 

@@ -622,6 +624,7 @@ InitPaging (
     NumberOfPdptEntries = 4;

   }

 

+  DisableReadOnlyPageWriteProtect (&WpEnabled, &CetEnabled);

   //

   // Go through page table and change 2MB-page into 4KB-page.

   //

@@ -802,6 +805,8 @@ InitPaging (
     } // end for PML4

   } // end for PML5

 

+  EnableReadOnlyPageWriteProtect (WpEnabled, CetEnabled);

+

   //

   // Flush TLB

   //