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| author | Ard Biesheuvel <ard.biesheuvel@linaro.org> | 2015-11-09 13:26:32 +0000 |
|---|---|---|
| committer | abiesheuvel <abiesheuvel@Edk2> | 2015-11-09 13:26:32 +0000 |
| commit | f97ab1bbf4c4512e1aabd149527c1aa4d5b0c03b (patch) | |
| tree | 55a182b6e3cc880ceb2ebdf9c0df3e2a035b3411 /ArmPkg/Include | |
| parent | acdb6dc8b739ccddd8425e609b68871151c5b94e (diff) | |
| download | edk2-f97ab1bbf4c4512e1aabd149527c1aa4d5b0c03b.zip edk2-f97ab1bbf4c4512e1aabd149527c1aa4d5b0c03b.tar.gz edk2-f97ab1bbf4c4512e1aabd149527c1aa4d5b0c03b.tar.bz2 | |
ArmPkg/ArmLib: remove CCSIDR based cache info routines
The ARM architecture does not allow the actual geometries of the caches
to be inferred from the CCSIDR cache info system register, since the
geometry it reports is intended for performing cache maintenance by
set/way and nothing else. Since the ArmLib cache info routines are
based solely on CCSIDR contents, they should not be used.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18753 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'ArmPkg/Include')
| -rw-r--r-- | ArmPkg/Include/Library/ArmLib.h | 78 |
1 files changed, 0 insertions, 78 deletions
diff --git a/ArmPkg/Include/Library/ArmLib.h b/ArmPkg/Include/Library/ArmLib.h index f1de303..2059a67 100644 --- a/ArmPkg/Include/Library/ArmLib.h +++ b/ArmPkg/Include/Library/ArmLib.h @@ -26,30 +26,6 @@ #error "Unknown chipset."
#endif
-typedef enum {
- ARM_CACHE_TYPE_WRITE_BACK,
- ARM_CACHE_TYPE_UNKNOWN
-} ARM_CACHE_TYPE;
-
-typedef enum {
- ARM_CACHE_ARCHITECTURE_UNIFIED,
- ARM_CACHE_ARCHITECTURE_SEPARATE,
- ARM_CACHE_ARCHITECTURE_UNKNOWN
-} ARM_CACHE_ARCHITECTURE;
-
-typedef struct {
- ARM_CACHE_TYPE Type;
- ARM_CACHE_ARCHITECTURE Architecture;
- BOOLEAN DataCachePresent;
- UINTN DataCacheSize;
- UINTN DataCacheAssociativity;
- UINTN DataCacheLineLength;
- BOOLEAN InstructionCachePresent;
- UINTN InstructionCacheSize;
- UINTN InstructionCacheAssociativity;
- UINTN InstructionCacheLineLength;
-} ARM_CACHE_INFO;
-
/**
* The UEFI firmware must not use the ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_* attributes.
*
@@ -126,66 +102,12 @@ typedef enum { #define GET_MPID(ClusterId, CoreId) (((ClusterId) << 8) | (CoreId))
#define PRIMARY_CORE_ID (PcdGet32(PcdArmPrimaryCore) & ARM_CORE_MASK)
-ARM_CACHE_TYPE
-EFIAPI
-ArmCacheType (
- VOID
- );
-
-ARM_CACHE_ARCHITECTURE
-EFIAPI
-ArmCacheArchitecture (
- VOID
- );
-
-VOID
-EFIAPI
-ArmCacheInformation (
- OUT ARM_CACHE_INFO *CacheInfo
- );
-
-BOOLEAN
-EFIAPI
-ArmDataCachePresent (
- VOID
- );
-
-UINTN
-EFIAPI
-ArmDataCacheSize (
- VOID
- );
-
-UINTN
-EFIAPI
-ArmDataCacheAssociativity (
- VOID
- );
-
UINTN
EFIAPI
ArmDataCacheLineLength (
VOID
);
-BOOLEAN
-EFIAPI
-ArmInstructionCachePresent (
- VOID
- );
-
-UINTN
-EFIAPI
-ArmInstructionCacheSize (
- VOID
- );
-
-UINTN
-EFIAPI
-ArmInstructionCacheAssociativity (
- VOID
- );
-
UINTN
EFIAPI
ArmInstructionCacheLineLength (
|