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2021-10-12tests/tcg: move some multiarch files and make conditionalAlex Bennée4-6/+15
We had some messy code to filter out stuff we can't build. Lets junk that and simplify the logic by pushing some stuff into subdirs. In particular we move: float_helpers into libs - not a standalone test linux-test into linux - so we only build on Linux hosts This allows for at least some of the tests to be nominally usable by *BSD user builds. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Cc: Warner Losh <imp@bsdimp.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Warner Losh <imp@bsdimp.com> Message-Id: <20210917162332.3511179-4-alex.bennee@linaro.org>
2021-10-12tests/tcg/sha1: remove endian includeAlex Bennée1-1/+0
This doesn't exist in BSD world and doesn't seem to be needed by either. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Warner Losh <imp@bsdimp.com> Message-Id: <20210917162332.3511179-3-alex.bennee@linaro.org>
2021-10-06Hexagon (target/hexagon) probe the stores in a packet at start of commitTaylor Simpson2-0/+107
When a packet has 2 stores, either both commit or neither commit. At the beginning of gen_commit_packet, we check for multiple stores. If there are multiple stores, call a helper that will probe each of them before proceeding with the commit. Note that we don't call the probe helper for packets with only one store. Therefore, we call process_store_log before anything else involved in committing the packet. We also fix a typo in the comment in process_store_log. Test case added in tests/tcg/hexagon/hex_sigsegv.c Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <1633036599-7637-1-git-send-email-tsimpson@quicinc.com>
2021-10-01tests/tcg/multiarch: Re-enable signals test for most guestsRichard Henderson4-11/+14
With signal trampolines safely off the stack for all guests besides hppa, we can re-enable this test. It does show up a problem with sh4 (unrelated?), so leave that test disabled for now. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210929130553.121567-27-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-09-06tests/tcg/s390x: Test SIGILL and SIGSEGV handlingIlya Leoshkevich3-1/+257
Verify that s390x-specific uc_mcontext.psw.addr is reported correctly and that signal handling interacts properly with debugging. Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Acked-by: Alex Bennée <alex.bennee@linaro.org> Acked-by: David Hildenbrand <david@redhat.com> Message-Id: <20210804225146.154513-1-iii@linux.ibm.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2021-09-02tests/plugins/insn: made arg inline not positional and parse it as boolMahmoud Mandour3-3/+3
Made argument "inline" not positional, this has two benefits. First is that we adhere to how QEMU passes args generally, by taking the last value of an argument and drop the others. And the second is that this sets up a framework for potentially adding new args easily. Signed-off-by: Mahmoud Mandour <ma.mandourr@gmail.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210730135817.17816-11-ma.mandourr@gmail.com> [AJB: fix check-tcg tests calling arg=inline] Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2021-09-01tests/tcg/riscv64: Add test for divisionRichard Henderson2-0/+63
Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210823195529.560295-3-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-08-26tests/tcg/multiarch/linux-test: Zero-initialize sockaddr structsPeter Maydell1-2/+2
Zero-initialize sockaddr_in and sockaddr_un structs that we're about to fill in and pass to bind() or connect(), to ensure we don't leave possible implementation-defined extension fields as uninitialized garbage. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Eric Blake <eblake@redhat.com> Message-id: 20210813150506.7768-5-peter.maydell@linaro.org
2021-08-03tests/tcg: Test that compare-and-trap raises SIGFPEJonathan Albrecht2-1/+103
Signed-off-by: Jonathan Albrecht <jonathan.albrecht@linux.vnet.ibm.com> Message-Id: <20210709160459.4962-3-jonathan.albrecht@linux.vnet.ibm.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2021-07-23tests/tcg/configure.sh: add handling for assembler only buildsAlex Bennée1-0/+18
Up until this point we only handled local compilers or assumed we had everything in the container. This falls down when we are building QEMU inside the container. This special handling only affects tricore for now but I put it in a case just in case we add any other "special" targets. Setting CROSS_CC_GUEST is a bit of a hack just to ensure the test runs as we gate on a detected compiler even though the Makefile won't actually use it. It also means we display something sane in the configure output. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210720232703.10650-27-alex.bennee@linaro.org>
2021-07-14tests/tcg: make test-mmap a little less aggressiveAlex Bennée2-113/+104
The check_aligned_anonymous_unfixed_mmaps and check_aligned_anonymous_unfixed_colliding_mmaps do a lot of mmap's and copying of data. This is especially unfriendly to targets like hexagon which have quite large pages and need to do sanity checks on each memory access. While we are at it clean-up the white space and style issues from the legacy code. As we no longer do quite so much needless memory access we can also remove the hexagon timeout hack. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <20210709143005.1554-27-alex.bennee@linaro.org>
2021-07-14tests/tcg: also disable the signals test for pluginsAlex Bennée2-0/+5
This will be more important when plugins is enabled by default. Fixes: eba61056e4 ("tests/tcg: generalise the disabling of the signals test") Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210709143005.1554-6-alex.bennee@linaro.org>
2021-07-08tests/tcg: generalise the disabling of the signals testAlex Bennée3-6/+6
It turns out you push down in one place and failures pop-up elsewhere. Especially on CI. Disable for now for all targets. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-06-29Hexagon (target/hexagon) fix l2fetch instructionsTaylor Simpson1-0/+9
Y4_l2fetch == l2fetch(Rs32, Rt32) Y5_l2fetch == l2fetch(Rs32, Rtt32) The semantics for these instructions are present, but the encodings are missing. Note that these are treated as nops in qemu, so we add overrides. Test case added to tests/tcg/hexagon/misc.c Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <1622589584-22571-3-git-send-email-tsimpson@quicinc.com>
2021-06-29Hexagon (target/hexagon) fix bug in fLSBNEW*Taylor Simpson1-1/+38
Change fLSBNEW/fLSBNEW0/fLSBNEW1 from copy to "x & 1" Remove gen_logical_not function Clean up fLSBNEWNOT to use andi-1 followed by xori-1 Test cases added to tests/tcg/hexagon/misc.c Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <1622589584-22571-2-git-send-email-tsimpson@quicinc.com>
2021-06-25tests/tcg: skip the signals test for hppa/s390x for nowAlex Bennée2-0/+8
There are fixes currently in flight but as this is getting in the way of a green CI we might as well skip for now. For reference the fix series are: linux-user: Move signal trampolines to new page 20210616011209.1446045-1-richard.henderson@linaro.org and linux-user: Load a vdso for x86_64 and hppa 20210619034329.532318-1-richard.henderson@linaro.org Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Acked-by: Cornelia Huck <cohuck@redhat.com> Cc: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210623102749.25686-7-alex.bennee@linaro.org>
2021-06-24Merge remote-tracking branch ↵Peter Maydell1-2/+2
'remotes/thuth-gitlab/tags/pull-request-2021-06-21' into staging * Documentation updates * Remove leading underscores from header guards * Display hexadecimal value with '0x' prefix # gpg: Signature made Mon 21 Jun 2021 11:33:53 BST # gpg: using RSA key 27B88847EEE0250118F3EAB92ED9D774FE702DB5 # gpg: issuer "thuth@redhat.com" # gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" [full] # gpg: aka "Thomas Huth <thuth@redhat.com>" [full] # gpg: aka "Thomas Huth <huth@tuxfamily.org>" [full] # gpg: aka "Thomas Huth <th.huth@posteo.de>" [unknown] # Primary key fingerprint: 27B8 8847 EEE0 2501 18F3 EAB9 2ED9 D774 FE70 2DB5 * remotes/thuth-gitlab/tags/pull-request-2021-06-21: MAINTAINERS: Add qtest/arm-cpu-features.c to ARM TCG CPUs section fuzz: Display hexadecimal value with '0x' prefix Remove leading underscores from QEMU defines Update documentation to refer to new location for issues docs/tools/virtiofsd: Fix bad rst syntax docs/tools/virtiofsd.rst: Do not hard-code the QEMU binary name docs/interop/live-block-operations: Do not hard-code the QEMU binary name Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-06-22Merge remote-tracking branch ↵Peter Maydell1-0/+9
'remotes/vivier2/tags/linux-user-for-6.1-pull-request' into staging Linux-user pull request 20210621 # gpg: Signature made Mon 21 Jun 2021 12:03:53 BST # gpg: using RSA key CD2F75DDC8E3A4DC2E4F5173F30C38BD3F2FBE3C # gpg: issuer "laurent@vivier.eu" # gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" [full] # gpg: aka "Laurent Vivier <laurent@vivier.eu>" [full] # gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" [full] # Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F 5173 F30C 38BD 3F2F BE3C * remotes/vivier2/tags/linux-user-for-6.1-pull-request: linux-user: Use public sigev_notify_thread_id member if available linux-user: Fix incorrect use of feature-test-macros linux-user: Check for ieee128 fpbits in PPC64 HWCAP2 feature list tests/tcg/linux-test: Check that sigaction can query SIGKILL/SIGSTOP linux-user: Let sigaction query SIGKILL/SIGSTOP linux-user: Implement pivot_root linux-user/trace-events: fix minor typo in format string linux-user: Disable static assert involving __SIGRTMAX if it is missing linux-user: Set CF_PARALLEL when mapping shared memory Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-06-21Remove leading underscores from QEMU definesAhmed Abouzied1-2/+2
Leading underscores followed by a capital letter or underscore are reserved by the C standard. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/369 Signed-off-by: Ahmed Abouzied <email@aabouzied.com> Message-Id: <20210605174938.13782-1-email@aabouzied.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2021-06-20tests/tcg/linux-test: Check that sigaction can query SIGKILL/SIGSTOPIlya Leoshkevich1-0/+9
Verify that querying is allowed, but making changes isn't. Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20210601145600.3131040-3-iii@linux.ibm.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-06-19tests/tcg: Increase timeout for TCIRichard Henderson1-2/+4
The longest test at the moment seems to be a (slower) aarch64 host, for which test-mmap takes 64 seconds. Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Acked-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-06-16target/arm: Fix mte page crossing testRichard Henderson2-1/+32
The test was off-by-one, because tag_last points to the last byte of the tag to check, thus tag_last - prev_page will equal TARGET_PAGE_SIZE when we use the first byte of the next page. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/403 Reported-by: Peter Collingbourne <pcc@google.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210612195707.840217-1-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-06-07tests/tcg/configure.sh: tweak quoting of target_compilerAlex Bennée1-3/+3
If you configure the host compiler with a multi-command stanza like: --cc="ccache gcc" then the configure.sh machinery falls over with confusion. Work around this by ensuring we correctly quote so where we need a complete evaluation we get it. Of course the has() check needs single variable so we need to unquote that. This does mean it essentially checks that just the ccache command exits but if we got past that step we still check the compiler actually does something. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Cc: Thomas Huth <thuth@redhat.com> Message-Id: <20210527160319.19834-4-alex.bennee@linaro.org>
2021-06-07tests/tcg: add a multiarch signals test to stress test signal deliveryAlex Bennée2-0/+151
This adds a simple signal test that combines the POSIX timer_create with signal delivery across multiple threads. The aim is to provide a bit more of a stress test to flush out signal handling issues for easily than the occasional random crash we sometimes see in linux-test or threadcount. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210527160319.19834-2-alex.bennee@linaro.org>
2021-05-20target/xtensa: clean up unaligned accessMax Filippov1-0/+221
Xtensa cores may or may not have hardware support for unaligned memory access. Remove TARGET_ALIGNED_ONLY=y from all xtensa configurations and pass MO_ALIGN in memory access flags for all operations that would raise an exception. Simplify use of gen_load_store_alignment by passing access size and alignment requirements in single parameter. Drop condition from xtensa_cpu_do_unaligned_access and replace it with assertion. Add a test. Suggested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Suggested-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2021-05-20tests/tcg/x86_64: add vsyscall smoke testIlya Leoshkevich2-1/+17
Having a small test will prevent trivial regressions in the future. Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Message-Id: <20210519045738.1335210-3-iii@linux.ibm.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2021-05-20Merge remote-tracking branch ↵Peter Maydell20-102/+492
'remotes/stsquad/tags/pull-testing-and-plugin-updates-180521-2' into staging testing and plugin updates: - various fixes for binfmt_misc docker images - add hexagon check-tcg support docker image - add tricore check-tcg support - refactor ppc docker images - add missing ppc64le tests - don't use host_cc for test fallback - check-tcg configure.sh tweaks for cross compile/clang - fix some memory leaks in plugins # gpg: Signature made Tue 18 May 2021 09:37:21 BST # gpg: using RSA key 6685AE99E75167BCAFC8DF35FBD0DB095A9E2A44 # gpg: Good signature from "Alex Bennée (Master Work Key) <alex.bennee@linaro.org>" [full] # Primary key fingerprint: 6685 AE99 E751 67BC AFC8 DF35 FBD0 DB09 5A9E 2A44 * remotes/stsquad/tags/pull-testing-and-plugin-updates-180521-2: (29 commits) configure: use cc, not host_cc to set cross_cc for build arch tests/tcg: don't allow clang as a cross compiler tests/tcg: fix missing return tests/tcg/ppc64le: tests for brh/brw/brd tests/docker: gcc-10 based images for ppc64{,le} tests tests/tcg/tricore: Add muls test tests/tcg/tricore: Add msub test tests/tcg/tricore: Add madd test tests/tcg/tricore: Add ftoi test tests/tcg/tricore: Add fmul test tests/tcg/tricore: Add fadd test tests/tcg/tricore: Add dvstep test tests/tcg/tricore: Add clz test tests/tcg/tricore: Add bmerge test tests/tcg/tricore: Add macros to create tests and first test 'abs' configure: Emit HOST_CC to config-host.mak tests/tcg/tricore: Add build infrastructure hw/tricore: Add testdevice for tests in tests/tcg/ tests/tcg: Run timeout cmds using --foreground tests/tcg: Add docker_as and docker_ld cmds ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-05-18tests/tcg: don't allow clang as a cross compilerAlex Bennée1-11/+22
Currently there are two problems. The first is clang generates a preamble (that is always executed) to stack xmm registers. This causes a ILLOP on the x86_64 softmmu tests as SSE isn't enabled. The second is the inline assembler in test-i386.c breaks clangs compiler and I don't know how to fix it. Even with Theodore's patch series (D5741445-7EFD-4AF1-8DB2-E4AFA93CBB1A@icloud.com) I still get compiler failures. For now lets just skip clang and allow it to fall back to the containers which we know have compilers which work. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210512102051.12134-31-alex.bennee@linaro.org>
2021-05-18tests/tcg: fix missing returnAlex Bennée1-0/+1
This was picked up when clang built the test. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210512102051.12134-30-alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2021-05-18tests/tcg/ppc64le: tests for brh/brw/brdMatheus Ferst3-0/+47
Tests for Byte-Reverse Halfword, Word and Doubleword Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Tested-by: Fabiano Rosas <farosas@linux.ibm.com> [AJB: tweak to make rules for skip/plugins] Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210423205757.1752480-3-matheus.ferst@eldorado.org.br> Message-Id: <20210512102051.12134-28-alex.bennee@linaro.org>
2021-05-18tests/docker: gcc-10 based images for ppc64{,le} testsMatheus Ferst1-10/+10
A newer compiler is needed to build tests for Power10 instructions. As done for arm64 on c729a99d2701, a new '-test-cross' image is created for ppc64 and ppc64le. As done on 936fda4d771f, a test for compiler support is added to verify that the toolchain in use has '-mpower10'. Finally, Unused images (docker-power-cross and docker-ppc64-cross) are removed. Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210423205757.1752480-2-matheus.ferst@eldorado.org.br> Message-Id: <20210512102051.12134-27-alex.bennee@linaro.org>
2021-05-18tests/tcg/tricore: Add muls testBastian Koppelmann2-0/+10
Tested-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210305170045.869437-16-kbastian@mail.uni-paderborn.de> Message-Id: <20210512102051.12134-26-alex.bennee@linaro.org>
2021-05-18tests/tcg/tricore: Add msub testBastian Koppelmann2-0/+10
Tested-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210305170045.869437-15-kbastian@mail.uni-paderborn.de> Message-Id: <20210512102051.12134-25-alex.bennee@linaro.org>
2021-05-18tests/tcg/tricore: Add madd testBastian Koppelmann3-0/+30
Tested-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210305170045.869437-14-kbastian@mail.uni-paderborn.de> Message-Id: <20210512102051.12134-24-alex.bennee@linaro.org>
2021-05-18tests/tcg/tricore: Add ftoi testBastian Koppelmann3-0/+18
Tested-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210305170045.869437-13-kbastian@mail.uni-paderborn.de> Message-Id: <20210512102051.12134-23-alex.bennee@linaro.org>
2021-05-18tests/tcg/tricore: Add fmul testBastian Koppelmann2-0/+9
Tested-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210305170045.869437-12-kbastian@mail.uni-paderborn.de> Message-Id: <20210512102051.12134-22-alex.bennee@linaro.org>
2021-05-18tests/tcg/tricore: Add fadd testBastian Koppelmann2-0/+17
Tested-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210305170045.869437-11-kbastian@mail.uni-paderborn.de> Message-Id: <20210512102051.12134-21-alex.bennee@linaro.org>
2021-05-18tests/tcg/tricore: Add dvstep testBastian Koppelmann3-1/+44
Tested-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210305170045.869437-10-kbastian@mail.uni-paderborn.de> Message-Id: <20210512102051.12134-20-alex.bennee@linaro.org>
2021-05-18tests/tcg/tricore: Add clz testBastian Koppelmann2-0/+10
Tested-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> [AJB: dropped duplicate Makefile] Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210305170045.869437-9-kbastian@mail.uni-paderborn.de> Message-Id: <20210512102051.12134-19-alex.bennee@linaro.org>
2021-05-18tests/tcg/tricore: Add bmerge testBastian Koppelmann3-0/+33
Tested-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210305170045.869437-8-kbastian@mail.uni-paderborn.de> Message-Id: <20210512102051.12134-18-alex.bennee@linaro.org>
2021-05-18tests/tcg/tricore: Add macros to create tests and first test 'abs'Bastian Koppelmann4-0/+68
This kind of tests is inspired by the riscv-tests repository. This adds macros that makes it easy to create single instruction self containing tests. It is achieved by macros that create a test sequence for an instruction and check for a supplied correct value. If the value is correct the next instruction is tested. Otherwise we jump to fail handler that writes is test number as a status code back to qemu that then exits on that status code. If all tests pass we write back 0 as a status code and exit. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-Id: <20210305170045.869437-7-kbastian@mail.uni-paderborn.de> [AJB: add container_hosts] Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210512102051.12134-17-alex.bennee@linaro.org>
2021-05-18tests/tcg/tricore: Add build infrastructureBastian Koppelmann2-0/+75
this includes the Makefile and linker script to build all the tests. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210305170045.869437-5-kbastian@mail.uni-paderborn.de> Message-Id: <20210512102051.12134-15-alex.bennee@linaro.org>
2021-05-18tests/tcg: Run timeout cmds using --foregroundBastian Koppelmann1-2/+3
when trying to run successful short tests from the Makefile timeout would not terminate. Rather it would wait until the time runs out. Excerpt from the manpage: --foreground when not running timeout directly from a shell prompt, allow COMMAND to read from the TTY and get TTY signals; in this mode, chil‐ dren of COMMAND will not be timed out Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210305170045.869437-3-kbastian@mail.uni-paderborn.de> Message-Id: <20210512102051.12134-13-alex.bennee@linaro.org>
2021-05-18tests/tcg: Add docker_as and docker_ld cmdsBastian Koppelmann2-1/+33
At least for the TriCore target no easily available c compiler exists. Thus we need to rely on "as" and "ld". This allows us to run them through the docker image. We don't test the generation capabilities of docker images as they are assumed to work. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> [AJB: fix quoting, only handle docker & clear, test -n, tweak commit msg] Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210512102051.12134-12-alex.bennee@linaro.org>
2021-05-18tests/tcg: don't iterate through other arch compilersAlex Bennée1-89/+59
There should only be one compiler per architecture. Those cases where the same compiler can deal with a different architecture should be explicitly set for both cross_cc and docker configurations. Otherwise you get strangeness like: --cross-cc-aarch64=/bin/false causing the logic to attempt to use a locally available arm-linux-gnueabihf-gcc rather than forcing the use of the docker image which is what is implied by the command line option. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210512102051.12134-10-alex.bennee@linaro.org>
2021-05-18tests/tcg: Use Hexagon Docker imageAlessandro Di Federico1-0/+5
[PMD: Split from 'Add Hexagon Docker image' patch] Signed-off-by: Alessandro Di Federico <ale@rev.ng> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> [AJB: add container_hosts] Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210228222314.304787-5-f4bug@amsat.org> Message-Id: <20210512102051.12134-8-alex.bennee@linaro.org>
2021-05-15tests/tcg/sparc64: Re-enable linux-testRichard Henderson1-6/+1
It passes now that we support signals properly. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210426025334.1168495-26-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-05-12Drop the deprecated lm32 targetMarkus Armbruster69-3220/+1
Target lm32 was deprecated in commit d8498005122, v5.2.0. See there for rationale. Some of its code lives on in device models derived from milkymist ones: hw/char/digic-uart.c and hw/display/bcm2835_fb.c. Cc: Michael Walle <michael@walle.cc> Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20210503084034.3804963-2-armbru@redhat.com> Acked-by: Michael Walle <michael@walle.cc> [Trivial conflicts resolved, reST markup fixed]
2021-05-01Hexagon (target/hexagon) CABAC decode binTaylor Simpson1-0/+28
The following instruction is added S2_cabacdecbin Rdd32=decbin(Rss32,Rtt32) Test cases added to tests/tcg/hexagon/misc.c Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <1617930474-31979-27-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-05-01Hexagon (target/hexagon) load into shifted register instructionsTaylor Simpson2-0/+416
The following instructions are added L2_loadalignb_io Ryy32 = memb_fifo(Rs32+#s11:1) L2_loadalignh_io Ryy32 = memh_fifo(Rs32+#s11:1) L4_loadalignb_ur Ryy32 = memb_fifo(Rt32<<#u2+#U6) L4_loadalignh_ur Ryy32 = memh_fifo(Rt32<<#u2+#U6) L4_loadalignb_ap Ryy32 = memb_fifo(Re32=#U6) L4_loadalignh_ap Ryy32 = memh_fifo(Re32=#U6) L2_loadalignb_pr Ryy32 = memb_fifo(Rx32++Mu2) L2_loadalignh_pr Ryy32 = memh_fifo(Rx32++Mu2) L2_loadalignb_pbr Ryy32 = memb_fifo(Rx32++Mu2:brev) L2_loadalignh_pbr Ryy32 = memh_fifo(Rx32++Mu2:brev) L2_loadalignb_pi Ryy32 = memb_fifo(Rx32++#s4:1) L2_loadalignh_pi Ryy32 = memh_fifo(Rx32++#s4:1) L2_loadalignb_pci Ryy32 = memb_fifo(Rx32++#s4:1:circ(Mu2)) L2_loadalignh_pci Ryy32 = memh_fifo(Rx32++#s4:1:circ(Mu2)) L2_loadalignb_pcr Ryy32 = memb_fifo(Rx32++I:circ(Mu2)) L2_loadalignh_pcr Ryy32 = memh_fifo(Rx32++I:circ(Mu2)) Test cases in tests/tcg/hexagon/load_align.c Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <1617930474-31979-26-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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