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2024-12-12tcg/riscv: Fix StoreStore barrier generationRoman Artemev1-1/+1
2024-12-12tcg: Reset free_temps before tcg_optimizeRichard Henderson1-1/+4
2024-11-16tcg: Allow top bit of SIMD_DATA_BITS to be set in simd_desc()Peter Maydell1-1/+14
2024-10-22tcg/ppc: Fix tcg_out_rlw_rcDani Szebenyi1-1/+3
2024-10-22tcg/riscv: Enable native vector support for TCG hostTANG Tiancheng1-3/+3
2024-10-22tcg/riscv: Implement vector roti/v/x opsTANG Tiancheng2-3/+39
2024-10-22tcg/riscv: Implement vector shi/s/v opsTANG Tiancheng3-3/+80
2024-10-22tcg/riscv: Implement vector min/max opsTANG Tiancheng2-1/+34
2024-10-22tcg/riscv: Implement vector sat/mul opsTANG Tiancheng2-2/+43
2024-10-22tcg/riscv: Accept constant first argument to sub_vecRichard Henderson2-2/+7
2024-10-22tcg/riscv: Implement vector neg opsTANG Tiancheng2-1/+8
2024-10-22tcg/riscv: Implement vector cmp/cmpsel opsTANG Tiancheng4-60/+200
2024-10-22tcg/riscv: Add support for basic vector opcodesTANG Tiancheng4-1/+85
2024-10-22tcg/riscv: Implement vector mov/dup{m/i}TANG Tiancheng1-2/+74
2024-10-22tcg/riscv: Add basic support for vectorHuang Shiyuan5-71/+436
2024-10-22tcg: Reset data_gen_ptr correctlyRichard Henderson1-1/+1
2024-10-17tcg/s390x: fix constraint for 32-bit TSTEQ/TSTNEPaolo Bonzini1-8/+16
2024-10-13include/exec/memop: Rename get_alignment_bitsRichard Henderson4-7/+7
2024-10-08tcg/ppc: Use TCG_REG_TMP2 for scratch index in prepare_host_addrRichard Henderson1-2/+2
2024-10-08tcg/ppc: Use TCG_REG_TMP2 for scratch tcg_out_qemu_stRichard Henderson1-2/+2
2024-09-28Merge tag 'pull-request-2024-09-25' of https://gitlab.com/thuth/qemu into sta...Peter Maydell1-1/+0
2024-09-27Merge tag 'pull-tcg-20240922' of https://gitlab.com/rth7680/qemu into stagingPeter Maydell17-407/+748
2024-09-24tcg/loongarch64: remove break after g_assert_not_reached()Pierrick Bouvier1-1/+0
2024-09-22tcg/s390x: Optimize cmpsel with constant 0/-1 argumentsRichard Henderson3-10/+34
2024-09-22tcg/s390x: Implement cmpsel_vecRichard Henderson3-20/+23
2024-09-22tcg/ppc: Optimize cmpsel with constant 0/-1 argumentsRichard Henderson2-12/+33
2024-09-22tcg/ppc: Implement cmpsel_vecRichard Henderson3-9/+54
2024-09-22tcg/i386: Implement vector TST{EQ,NE} for avx512Richard Henderson2-4/+29
2024-09-22tcg/i386: Implement cmpsel_vec with avx512 insnsRichard Henderson1-1/+43
2024-09-22tcg/i386: Add predicate parameters to tcg_out_evex_opcRichard Henderson1-2/+4
2024-09-22tcg/i386: Implement cmp_vec with avx512 insnsRichard Henderson1-1/+63
2024-09-22tcg/i386: Optimize cmpsel with constant 0 operand 3.Richard Henderson3-8/+27
2024-09-22tcg/optimize: Optimize bitsel_vecRichard Henderson1-0/+58
2024-09-22tcg/optimize: Optimize cmp_vec and cmpsel_vecRichard Henderson1-0/+36
2024-09-22tcg/optimize: Fold movcond with true and false values identicalRichard Henderson1-0/+5
2024-09-22tcg/s390x: Do not expand cmp_vec earlyRichard Henderson1-74/+65
2024-09-22tcg/ppc: Do not expand cmp_vec earlyRichard Henderson1-79/+90
2024-09-22tcg/i386: Do not expand cmpsel_vec earlyRichard Henderson4-34/+52
2024-09-22tcg/i386: Do not expand cmp_vec earlyRichard Henderson1-123/+100
2024-09-22tcg/i386: Split out tcg_out_vex_modrm_typeRichard Henderson1-23/+15
2024-09-22tcg: Export vec_gen_6Richard Henderson2-2/+4
2024-09-22tcg: Fix iteration step in 32-bit gvec operationTANG Tiancheng1-1/+1
2024-09-22tcg: Propagate new TCGOp to add_as_label_useRichard Henderson1-31/+32
2024-09-22tcg: Return TCGOp from tcg_gen_op[1-6]Richard Henderson2-14/+21
2024-09-19plugins: save value during memory accessesPierrick Bouvier1-7/+59
2024-08-08tcg/ppc: Sync tcg_out_test and constraintsRichard Henderson1-11/+10
2024-07-04Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into stagingRichard Henderson1-4/+4
2024-07-03tcg/optimize: Fix TCG_COND_TST* simplification of setcond2Richard Henderson1-1/+1
2024-07-03util/cpuinfo-riscv: Support host/cpuinfo.h for riscvRichard Henderson2-101/+29
2024-07-03meson: Drop the .fa library suffixPaolo Bonzini1-2/+0
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