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| author | Richard Henderson <richard.henderson@linaro.org> | 2024-10-05 22:09:54 +0000 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2024-10-08 06:40:31 -0700 |
| commit | 3213da7b9539581c6df95f8ced5b09d0b02d425f (patch) | |
| tree | 08c836257dc2be2c7be79659198a07c79461f406 /tcg | |
| parent | 4cabcb89b101942346aebff081aa1453e958fe7f (diff) | |
| download | qemu-3213da7b9539581c6df95f8ced5b09d0b02d425f.zip qemu-3213da7b9539581c6df95f8ced5b09d0b02d425f.tar.gz qemu-3213da7b9539581c6df95f8ced5b09d0b02d425f.tar.bz2 | |
tcg/ppc: Use TCG_REG_TMP2 for scratch index in prepare_host_addr
In tcg_out_qemu_ldst_i128, we need a non-zero index register,
which we then use as a base register in several address modes.
Since we always have TCG_REG_TMP2 available, use that.
Cc: qemu-stable@nongnu.org
Fixes: 526cd4ec01f ("tcg/ppc: Support 128-bit load/store")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2597
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Tested-By: Michael Tokarev <mjt@tls.msk.ru>
Diffstat (limited to 'tcg')
| -rw-r--r-- | tcg/ppc/tcg-target.c.inc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 6be5049..223f079 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -2617,8 +2617,8 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, if (TCG_TARGET_REG_BITS == 64 && addr_type == TCG_TYPE_I32) { /* Zero-extend the guest address for use in the host address. */ - tcg_out_ext32u(s, TCG_REG_R0, addrlo); - h->index = TCG_REG_R0; + tcg_out_ext32u(s, TCG_REG_TMP2, addrlo); + h->index = TCG_REG_TMP2; } else { h->index = addrlo; } |