aboutsummaryrefslogtreecommitdiff
path: root/tcg/riscv
AgeCommit message (Expand)AuthorFilesLines
2022-01-08exec/memop: Adding signedness to quad definitionsFrédéric Pétrot1-3/+3
2021-10-05tcg: Rename TCGMemOpIdx to MemOpIdxRichard Henderson1-8/+8
2021-10-05tcg: Expand MO_SIZE to 3 bitsRichard Henderson1-2/+2
2021-09-21tcg/riscv: Remove add with zero on user-only memory accessRichard Henderson1-8/+2
2021-07-09tcg: Remove TCG_TARGET_HAS_goto_ptrRichard Henderson1-1/+0
2021-06-29tcg/riscv: Remove MO_BSWAP handlingRichard Henderson1-31/+33
2021-06-11tcg: Move MAX_CODE_GEN_BUFFER_SIZE to tcg-target.hRichard Henderson1-0/+1
2021-06-04tcg: Change parameters for tcg_target_const_matchRichard Henderson1-3/+1
2021-03-17tcg: Fix prototypes for tcg_out_vec_op and tcg_out_opMiroslav Rezanina1-1/+2
2021-02-02tcg: Remove TCG_TARGET_CON_SET_HRichard Henderson1-1/+0
2021-02-02tcg/riscv: Split out constraint sets to tcg-target-con-set.hRichard Henderson3-60/+54
2021-02-02tcg: Remove TCG_TARGET_CON_STR_HRichard Henderson1-1/+0
2021-02-02tcg/riscv: Split out target constraints to tcg-target-con-str.hRichard Henderson3-39/+35
2021-01-13tcg: Remove movi and dupi opcodesRichard Henderson1-2/+0
2021-01-07tcg: Constify TCGLabelQemuLdst.raddrRichard Henderson1-2/+1
2021-01-07tcg: Constify tcg_code_gen_epilogueRichard Henderson1-2/+1
2021-01-07tcg: Remove TCG_TARGET_SUPPORT_MIRRORRichard Henderson1-1/+0
2021-01-07tcg/riscv: Support split-wx code generationRichard Henderson2-19/+24
2021-01-07tcg/riscv: Remove branch-over-branch fallbackRichard Henderson1-50/+6
2021-01-07tcg/riscv: Fix branch range checksRichard Henderson1-13/+15
2021-01-07tcg: Add --accel tcg,split-wx propertyRichard Henderson1-0/+1
2021-01-07tcg: Adjust tb_target_set_jmp_target for split-wxRichard Henderson1-1/+1
2021-01-07tcg: Adjust tcg_register_jit for constRichard Henderson1-1/+1
2021-01-07tcg: Adjust tcg_out_call for constRichard Henderson1-3/+3
2021-01-07tcg: Move tcg epilogue pointer out of TCGContextRichard Henderson1-2/+2
2021-01-07tcg: Introduce INDEX_op_qemu_st8_i32Richard Henderson1-0/+1
2021-01-06Merge remote-tracking branch 'remotes/bonzini-gitlab/tags/for-upstream' into ...Peter Maydell1-5/+0
2021-01-04tcg/riscv: Fix illegal shift instructionsZihao Yu1-6/+6
2021-01-02util: Extract flush_icache_range to cacheflush.cRichard Henderson1-5/+0
2020-10-08tcg: Remove TCG_CT_REGRichard Henderson1-2/+0
2020-10-08tcg: Drop union from TCGArgConstraintRichard Henderson1-7/+7
2020-08-21meson: rename included C source files to .c.incPaolo Bonzini1-2/+2
2020-07-13tcg/riscv: Remove superfluous breaksLiao Pingfang1-2/+0
2020-01-15tcg: Search includes in the parent source directoryPhilippe Mathieu-Daudé1-2/+2
2019-09-03tcg: TCGMemOp is now accelerator independent MemOpTony Nguyen1-10/+10
2019-07-09tcg/riscv: Fix RISC-VH host build failureAlistair Francis1-2/+2
2019-06-10cpu: Move the softmmu tlb to CPUNegativeOffsetStateRichard Henderson1-24/+7
2019-06-10tcg: Create struct CPUTLBRichard Henderson1-10/+2
2019-05-13tcg: Return bool success from tcg_out_movRichard Henderson1-2/+3
2019-04-24tcg: Restart TB generation after out-of-line ldst overflowRichard Henderson1-4/+12
2019-04-24tcg: Add INDEX_op_extract2_{i32,i64}Richard Henderson1-0/+2
2019-01-28cputlb: Remove static tlb sizingRichard Henderson1-1/+0
2019-01-28tcg/riscv: enable dynamic TLB sizingRichard Henderson2-71/+55
2019-01-28tcg: introduce dynamic TLB sizingEmilio G. Cota1-0/+1
2018-12-26tcg/riscv: Add the target init codeAlistair Francis1-0/+31
2018-12-26tcg/riscv: Add the prologue generation and register the JITAlistair Francis1-0/+111
2018-12-26tcg/riscv: Add the out op decoderAlistair Francis1-0/+496
2018-12-26tcg/riscv: Add direct load and store instructionsAlistair Francis1-0/+158
2018-12-26tcg/riscv: Add slowpath load and store instructionsAlistair Francis1-0/+256
2018-12-26tcg/riscv: Add branch and jump instructionsAlistair Francis1-0/+145
generated by cgit v1.1 at 2024-11-01 20:11:40 +0000