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6 daystcg/ppc: Optimize cmpsel with constant 0/-1 argumentsRichard Henderson2-12/+33
These can be simplified to and/or/andc/orc, avoiding the load of the constantinto a register. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6 daystcg/ppc: Implement cmpsel_vecRichard Henderson3-9/+54
Do not allow cmpsel_vec to be expanded early, so that we can make the correct decision wrt the sense of the comparison. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6 daystcg/ppc: Do not expand cmp_vec earlyRichard Henderson1-79/+90
Move expansion to opcode generation. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-08-08tcg/ppc: Sync tcg_out_test and constraintsRichard Henderson1-11/+10
Ensure the code structure is the same for matching constraints and emitting code, lest we allow constants that cannot be trivially tested. Cc: qemu-stable@nongnu.org Fixes: ad788aebbab ("tcg/ppc: Support TCG_COND_TST{EQ,NE}") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2487 Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <44328324-af73-4439-9d2b-d414e0e13dd7@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-05-22tcg: Introduce TCG_TARGET_HAS_tst_vecRichard Henderson1-0/+1
Prelude to supporting TCG_COND_TST* in vector comparisons. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-02-03tcg/ppc: Support TCG_COND_TST{EQ,NE}Richard Henderson2-9/+115
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-02-03tcg/ppc: Add TCG_CT_CONST_CMPRichard Henderson3-10/+44
Better constraint for tcg_out_cmp, based on the comparison. We can't yet remove the fallback to load constants into a scratch because of tcg_out_cmp2, but that path should not be as frequent. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-02-03tcg/ppc: Tidy up tcg_target_const_matchRichard Henderson1-11/+16
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-02-03tcg/ppc: Use cr0 in tcg_to_bc and tcg_to_iselRichard Henderson1-34/+34
Using cr0 means we could choose to use rc=1 to compute the condition. Adjust the tables and tcg_out_cmp that feeds them. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-02-03tcg/ppc: Sink tcg_to_bc usage into tcg_out_bcRichard Henderson1-11/+17
Rename the current tcg_out_bc function to tcg_out_bc_lab, and create a new function that takes an integer displacement + link. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-02-03tcg: Add TCGConst argument to tcg_target_const_matchRichard Henderson1-1/+2
Fill the new argument from any condition within the opcode. Not yet used within any backend. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-02-03tcg: Introduce TCG_TARGET_HAS_tstRichard Henderson1-0/+2
Define as 0 for all tcg backends. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-01-11tcg/ppc: Use new registers for LQ destinationRichard Henderson2-2/+3
LQ has a constraint that RTp != RA, else SIGILL. Therefore, force the destination of INDEX_op_qemu_*_ld128 to be a new register pair, so that it cannot overlap the input address. This requires new support in process_op_defs and tcg_reg_alloc_op. Cc: qemu-stable@nongnu.org Fixes: 526cd4ec01f ("tcg/ppc: Support 128-bit load/store") Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20240102013456.131846-1-richard.henderson@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06tcg: Remove TCG_TARGET_HAS_neg_{i32,i64}Richard Henderson1-2/+0
The movcond opcode is now mandatory for backends to implement. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231026041404.1229328-7-richard.henderson@linaro.org>
2023-11-06tcg: Remove TCG_TARGET_HAS_movcond_{i32,i64}Richard Henderson1-2/+0
The movcond opcode is now mandatory for backends to implement. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231026041404.1229328-4-richard.henderson@linaro.org>
2023-10-22tcg/ppc: Use tcg_use_softmmuRichard Henderson1-127/+129
Fix TCG_GUEST_BASE_REG to use 'TCG_REG_R30' instead of '30'. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-22tcg/ppc: Disable TCG_REG_TB for Power9/Power10Richard Henderson1-1/+1
This appears to slightly improve performance on power9/10. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-22tcg/ppc: Use PLD in tcg_out_goto_tbRichard Henderson1-0/+3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-22tcg/ppc: Use prefixed instructions in tcg_out_dupi_vecRichard Henderson1-0/+9
The prefixed instructions have a pc-relative form to use here. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-22tcg/ppc: Use PLD in tcg_out_movi for constant poolRichard Henderson1-0/+24
The prefixed instruction has a pc-relative form to use here. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-22tcg/ppc: Use prefixed instructions in tcg_out_mem_longRichard Henderson1-0/+66
When the offset is out of range of the non-prefixed insn, but fits the 34-bit immediate of the prefixed insn, use that. Reviewed-by: Jordan Niethe <jniethe5@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-22tcg/ppc: Use PADDI in tcg_out_moviRichard Henderson1-0/+51
PADDI can load 34-bit immediates and 34-bit pc-relative addresses. Reviewed-by: Jordan Niethe <jniethe5@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-22tcg/ppc: Use ADDPCIS in tcg_out_goto_tbRichard Henderson1-2/+9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-22tcg/ppc: Use ADDPCIS for the constant poolRichard Henderson1-0/+12
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-22tcg/ppc: Use ADDPCIS in tcg_out_movi_intRichard Henderson1-0/+13
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-22tcg/ppc: Use ADDPCIS in tcg_out_tb_startRichard Henderson1-3/+22
With ISA v3.0, we can use ADDPCIS instead of BCL+MFLR to load NIA. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-22tcg/ppc: Reinterpret tb-relative to TB+4Richard Henderson1-5/+10
It saves one insn to load the address of TB+4 instead of TB. Adjust all of the indexing to match. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-22tcg/ppc: Enable direct branching tcg_out_goto_tb with TCG_REG_TBJordan Niethe1-31/+17
Direct branch patching was disabled when using TCG_REG_TB in commit 736a1588c1 ("tcg/ppc: Fix race in goto_tb implementation"). The issue with direct branch patching with TCG_REG_TB is the lack of synchronization between the new TCG_REG_TB being established and the direct branch being patched in. If each translation block is responsible for establishing its own TCG_REG_TB then there can be no synchronization issue. Make each translation block begin by setting up its own TCG_REG_TB. Use the preferred 'bcl 20,31,$+4' sequence. Signed-off-by: Jordan Niethe <jniethe5@gmail.com> [rth: Split out tcg_out_tb_start, power9 addpcis] Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-22tcg/ppc: Untabify tcg-target.c.incRichard Henderson1-3/+3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-07tcg: Correct invalid mentions of 'softmmu' by 'system-mode'Philippe Mathieu-Daudé1-2/+2
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20231004090629.37473-6-philmd@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-09-16tcg: Add tcg_out_tb_start backend hookRichard Henderson1-0/+5
This hook may emit code at the beginning of the TB. Suggested-by: Jordan Niethe <jniethe5@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-09-15tcg: pass vece to tcg_target_const_match()Jiajie Chen1-1/+1
Pass vece to tcg_target_const_match() to allow correct interpretation of const args of vector ops. Signed-off-by: Jiajie Chen <c@jia.je> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230908022302.180442-4-c@jia.je> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-08-24tcg/ppc: Use the Set Boolean ExtensionRichard Henderson1-0/+22
The SETBC family of instructions requires exactly two insns for all comparisions, saving 0-3 insns per (neg)setcond. Tested-by: Nicholas Piggin <npiggin@gmail.com> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-08-24tcg/ppc: Implement negsetcond_*Richard Henderson2-49/+82
In the general case we simply negate. However with isel we may load -1 instead of 1 with no extra effort. Consolidate EQ0 and NE0 logic. Replace the NE0 zero-extension with inversion+negation of EQ0, which is never worse and may eliminate one insn. Provide a special case for -EQ0. Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-08-24tcg: Introduce negsetcond opcodesRichard Henderson1-0/+2
Introduce a new opcode for negative setcond. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-08-24tcg: Unify TCG_TARGET_HAS_extr[lh]_i64_i32Richard Henderson1-2/+1
Replace the separate defines with TCG_TARGET_HAS_extr_i64_i32, so that the two parts of backend-specific type changing cannot be out of sync. Reported-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: <20230822175127.1173698-1-richard.henderson@linaro.org>
2023-07-23tcg/ppc: Fix race in goto_tb implementationJordan Niethe1-4/+5
Commit 20b6643324 ("tcg/ppc: Reorg goto_tb implementation") modified goto_tb to ensure only a single instruction was patched to prevent incorrect behavior if a thread was in the middle of multiple instructions when they were replaced. However this introduced a race between loading the jmp target into TCG_REG_TB and patching and executing the direct branch. The relevant part of the goto_tb implementation: ld TCG_REG_TB, TARGET_ADDR_LOCATION(TCG_REG_TB) patch_location: mtctr TCG_REG_TB bctr tb_target_set_jmp_target() will replace 'patch_location' with a direct branch if the target is in range. The direct branch now relies on TCG_REG_TB being set up correctly by the ld. Prior to this commit multiple instructions were patched in for the direct branch case; these instructions would initialize TCG_REG_TB to the same value as the branch target. Imagine the following sequence: 1) Thread A is executing the goto_tb sequence and loads the jmp target into TCG_REG_TB. 2) Thread B updates the jmp target address and calls tb_target_set_jmp_target(). This patches a new direct branch into the goto_tb sequence. 3) Thread A executes the newly patched direct branch. The value in TCG_REG_TB still contains the old jmp target. TCG_REG_TB MUST contain the translation block's tc.ptr. Execution will eventually crash after performing memory accesses generated from a faulty value in TCG_REG_TB. This presents as segfaults or illegal instruction exceptions. Do not revert commit 20b6643324 as it did fix a different race condition. Instead remove the direct branch optimization and always use indirect branches. The direct branch optimization can be re-added later with a race free sequence. Fixes: 20b6643324 ("tcg/ppc: Reorg goto_tb implementation") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1726 Reported-by: Anushree Mathur <anushree.mathur@linux.vnet.ibm.com> Tested-by: Anushree Mathur <anushree.mathur@linux.vnet.ibm.com> Tested-by: Michael Tokarev <mjt@tls.msk.ru> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Co-developed-by: Benjamin Gray <bgray@linux.ibm.com> Signed-off-by: Jordan Niethe <jniethe5@gmail.com> Signed-off-by: Benjamin Gray <bgray@linux.ibm.com> Message-Id: <20230717093001.13167-1-jniethe5@gmail.com>
2023-07-08util: Add cpuinfo-ppc.cRichard Henderson2-51/+9
Move the code from tcg/. Fix a bug in that PPC_FEATURE2_ARCH_3_10 is actually spelled PPC_FEATURE2_ARCH_3_1. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-06-20tcg/ppc: Define _CALL_AIX for clang on ppc64(be)Richard Henderson1-7/+16
Restructure the ifdef ladder, separating 64-bit from 32-bit, and ensure _CALL_AIX is set for ELF v1. Fixes the build for ppc64 big-endian host with clang. Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-06-05tcg: Split out tcg-target-reg-bits.hRichard Henderson2-5/+16
Often, the only thing we need to know about the TCG host is the register size. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-06-05tcg: Add tlb_fast_offset to TCGContextRichard Henderson1-3/+4
Disconnect the layout of ArchCPU from TCG compilation. Pass the relative offset of 'env' and 'neg.tlb.f' as a parameter. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-06-05tcg: Widen CPUTLBEntry comparators to 64-bitsRichard Henderson1-12/+16
This makes CPUTLBEntry agnostic to the address size of the guest. When 32-bit addresses are in effect, we can simply read the low 32 bits of the 64-bit field. Similarly when we need to update the field for setting TLB_NOTDIRTY. For TCG backends that could in theory be big-endian, but in practice are not (arm, loongarch, riscv), use QEMU_BUILD_BUG_ON to document and ensure this is not accidentally missed. For s390x, which is always big-endian, use HOST_BIG_ENDIAN anyway, to document the reason for the adjustment. For sparc64 and ppc64, always perform a 64-bit load, and rely on the following 32-bit comparison to ignore the high bits. Rearrange mips and ppc if ladders for clarity. Reviewed-by: Anton Johansson <anjo@rev.ng> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-06-05tcg/ppc: Remove TARGET_LONG_BITS, TCG_TYPE_TLRichard Henderson1-10/+11
All uses replaced with TCGContext.addr_type. Reviewed-by: Anton Johansson <anjo@rev.ng> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-05-30tcg: Remove TCG_TARGET_TLB_DISPLACEMENT_BITSRichard Henderson1-1/+0
The last use was removed by e77c89fb086a. Fixes: e77c89fb086a ("cputlb: Remove static tlb sizing") Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-05-30tcg/ppc: Support 128-bit load/storeRichard Henderson4-13/+101
Use LQ/STQ with ISA v2.07, and 16-byte atomicity is required. Note that these instructions do not require 16-byte alignment. Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-05-16tcg: Add page_bits and page_mask to TCGContextRichard Henderson1-7/+7
Disconnect guest page size from TCG compilation. While this could be done via exec/target_page.h, we want to cache the value across multiple memory access operations, so we might as well initialize this early. The changes within tcg/ are entirely mechanical: sed -i s/TARGET_PAGE_BITS/s->page_bits/g sed -i s/TARGET_PAGE_MASK/s->page_mask/g Reviewed-by: Anton Johansson <anjo@rev.ng> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-05-16tcg: Split INDEX_op_qemu_{ld,st}* for guest address sizeRichard Henderson1-33/+46
For 32-bit hosts, we cannot simply rely on TCGContext.addr_bits, as we need one or two host registers to represent the guest address. Create the new opcodes and update all users. Since we have not yet eliminated TARGET_LONG_BITS, only one of the two opcodes will ever be used, so we can get away with treating them the same in the backends. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-05-16tcg/ppc: Use atom_and_align_for_opcRichard Henderson1-1/+18
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-05-16tcg: Add INDEX_op_qemu_{ld,st}_i128Richard Henderson1-0/+2
Add opcodes for backend support for 128-bit memory operations. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-05-16tcg: Introduce tcg_target_has_memory_bswapRichard Henderson2-1/+5
Replace the unparameterized TCG_TARGET_HAS_MEMORY_BSWAP macro with a function with a memop argument. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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