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2024-10-13tcg: remove singlestep_enabled from DisasContextBasePaolo Bonzini1-2/+3
It is used in a couple of places only, both within the same target. Those can use the cflags just as well, so remove the separate field. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Message-ID: <20241010083641.1785069-1-pbonzini@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-10-08target/m68k: Always return a temporary from gen_lea_modeRichard Henderson1-4/+9
Returning a raw areg does not preserve the value if the areg is subsequently modified. Fixes, e.g. "jsr (sp)", where the return address is pushed before the branch. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2483 Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240813000737.228470-1-richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-10-07target/s390x: Use explicit big-endian LD/ST APIPhilippe Mathieu-Daudé2-18/+18
The S390X architecture uses big endianness. Directly use the big-endian LD/ST API. Mechanical change using: $ end=be; \ for acc in uw w l q tul; do \ sed -i -e "s/ld${acc}_p(/ld${acc}_${end}_p(/" \ -e "s/st${acc}_p(/st${acc}_${end}_p(/" \ $(git grep -wlE '(ld|st)t?u?[wlq]_p' target/s390x/); \ done Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-ID: <20241004163042.85922-24-philmd@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2024-10-07target/s390x: Replace ldtul_p() -> ldq_p()Philippe Mathieu-Daudé1-15/+15
The S390X target is only built for 64-bit. Using ldtul_p() is pointless, replace by ldq_p(). Mechanical change doing: $ sed -i -e 's/ldtul_p/ldq_p/' $(git grep -wl ldtul_p target/s390x/) Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20241004163042.85922-5-philmd@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2024-10-07target/m68k: Use explicit big-endian LD/ST APIPhilippe Mathieu-Daudé2-6/+6
The M68K architecture uses big endianness. Directly use the big-endian LD/ST API. Mechanical change using: $ end=be; \ for acc in uw w l q tul; do \ sed -i -e "s/ld${acc}_p(/ld${acc}_${end}_p(/" \ -e "s/st${acc}_p(/st${acc}_${end}_p(/" \ $(git grep -wlE '(ld|st)t?u?[wlq]_p' target/m68k/); \ done Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <huth@tuxfamily.org> Message-ID: <20241004163042.85922-19-philmd@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2024-10-04Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into stagingPeter Maydell11-168/+267
* pc: Add a description for the i8042 property * kvm: support for nested FRED * tests/unit: fix warning when compiling test-nested-aio-poll with LTO * kvm: refactoring of VM creation * target/i386: expose IBPB-BRTYPE and SBPB CPUID bits to the guest * hw/char: clean up serial * remove virtfs-proxy-helper * target/i386/kvm: Report which action failed in kvm_arch_put/get_registers * qom: improvements to object_resolve_path*() # -----BEGIN PGP SIGNATURE----- # # iQFIBAABCAAyFiEE8TM4V0tmI4mGbHaCv/vSX3jHroMFAmb++MsUHHBib256aW5p # QHJlZGhhdC5jb20ACgkQv/vSX3jHroPVnwf/cdvfxvDm22tEdlh8vHlV17HtVdcC # Hw334M/3PDvbTmGzPBg26lzo4nFS6SLrZ8ETCeqvuJrtKzqVk9bI8ssZW5KA4ijM # nkxguRPHO8E6U33ZSucc+Hn56+bAx4I2X80dLKXJ87OsbMffIeJ6aHGSEI1+fKVh # pK7q53+Y3lQWuRBGhDIyKNuzqU4g+irpQwXOhux63bV3ADadmsqzExP6Gmtl8OKM # DylPu1oK7EPZumlSiJa7Gy1xBqL4Rc4wGPNYx2RVRjp+i7W2/Y1uehm3wSBw+SXC # a6b7SvLoYfWYS14/qCF4cBL3sJH/0f/4g8ZAhDDxi2i5kBr0/5oioDyE/A== # =/zo4 # -----END PGP SIGNATURE----- # gpg: Signature made Thu 03 Oct 2024 21:04:27 BST # gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83 # gpg: issuer "pbonzini@redhat.com" # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full] # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full] # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * tag 'for-upstream' of https://gitlab.com/bonzini/qemu: (23 commits) qom: update object_resolve_path*() documentation qom: set *ambiguous on all paths qom: rename object_resolve_path_type() "ambiguousp" target/i386/kvm: Report which action failed in kvm_arch_put/get_registers kvm: Allow kvm_arch_get/put_registers to accept Error** accel/kvm: refactor dirty ring setup minikconf: print error entirely on stderr 9p: remove 'proxy' filesystem backend driver hw/char: Extract serial-mm hw/char/serial.h: Extract serial-isa.h hw: Remove unused inclusion of hw/char/serial.h target/i386: Expose IBPB-BRTYPE and SBPB CPUID bits to the guest kvm: refactor core virtual machine creation into its own function kvm/i386: replace identity_base variable with a constant kvm/i386: refactor kvm_arch_init and split it into smaller functions kvm: replace fprintf with error_report()/printf() in kvm_init() kvm/i386: fix return values of is_host_cpu_intel() kvm/i386: make kvm_filter_msr() and related definitions private to kvm module hw/i386/pc: Add a description for the i8042 property tests/unit: remove block layer code from test-nested-aio-poll ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org> # Conflicts: # hw/arm/Kconfig # hw/arm/pxa2xx.c
2024-10-03target/i386/kvm: Report which action failed in kvm_arch_put/get_registersJulia Suvorova1-0/+23
To help debug and triage future failure reports (akin to [1,2]) that may occur during kvm_arch_put/get_registers, the error path of each action is accompanied by unique error message. [1] https://issues.redhat.com/browse/RHEL-7558 [2] https://issues.redhat.com/browse/RHEL-21761 Signed-off-by: Julia Suvorova <jusual@redhat.com> Reviewed-by: Peter Xu <peterx@redhat.com> Link: https://lore.kernel.org/r/20240927104743.218468-3-jusual@redhat.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2024-10-03kvm: Allow kvm_arch_get/put_registers to accept Error**Julia Suvorova7-14/+14
This is necessary to provide discernible error messages to the caller. Signed-off-by: Julia Suvorova <jusual@redhat.com> Reviewed-by: Peter Xu <peterx@redhat.com> Link: https://lore.kernel.org/r/20240927104743.218468-2-jusual@redhat.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2024-10-03target/i386: Expose IBPB-BRTYPE and SBPB CPUID bits to the guestFabiano Rosas1-2/+2
According to AMD's Speculative Return Stack Overflow whitepaper (link below), the hypervisor should synthesize the value of IBPB_BRTYPE and SBPB CPUID bits to the guest. Support for this is already present in the kernel with commit e47d86083c66 ("KVM: x86: Add SBPB support") and commit 6f0f23ef76be ("KVM: x86: Add IBPB_BRTYPE support"). Add support in QEMU to expose the bits to the guest OS. host: # cat /sys/devices/system/cpu/vulnerabilities/spec_rstack_overflow Mitigation: Safe RET before (guest): $ cpuid -l 0x80000021 -1 -r 0x80000021 0x00: eax=0x00000045 ebx=0x00000000 ecx=0x00000000 edx=0x00000000 ^ $ cat /sys/devices/system/cpu/vulnerabilities/spec_rstack_overflow Vulnerable: Safe RET, no microcode after (guest): $ cpuid -l 0x80000021 -1 -r 0x80000021 0x00: eax=0x18000045 ebx=0x00000000 ecx=0x00000000 edx=0x00000000 ^ $ cat /sys/devices/system/cpu/vulnerabilities/spec_rstack_overflow Mitigation: Safe RET Reported-by: Fabian Vogt <fvogt@suse.de> Link: https://www.amd.com/content/dam/amd/en/documents/corporate/cr/speculative-return-stack-overflow-whitepaper.pdf Signed-off-by: Fabiano Rosas <farosas@suse.de> Link: https://lore.kernel.org/r/20240805202041.5936-1-farosas@suse.de Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2024-10-03kvm/i386: replace identity_base variable with a constantPaolo Bonzini1-18/+18
identity_base variable is first initialzied to address 0xfffbc000 and then kvm_vm_set_identity_map_addr() overrides this value to address 0xfeffc000. The initial address to which the variable was initialized was never used. Clean everything up, placing 0xfeffc000 in a preprocessor constant. Reported-by: Ani Sinha <anisinha@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2024-10-03kvm/i386: refactor kvm_arch_init and split it into smaller functionsAni Sinha1-126/+201
kvm_arch_init() enables a lot of vm capabilities. Refactor them into separate smaller functions. Energy MSR related operations also moved to its own function. There should be no functional impact. Signed-off-by: Ani Sinha <anisinha@redhat.com> Link: https://lore.kernel.org/r/20240903124143.39345-2-anisinha@redhat.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2024-10-03Merge tag 'warn-pull-request' of https://gitlab.com/marcandre.lureau/qemu ↵Peter Maydell1-12/+14
into staging -Werror=maybe-uninitialized fixes # -----BEGIN PGP SIGNATURE----- # # iQJQBAABCAA6FiEEh6m9kz+HxgbSdvYt2ujhCXWWnOUFAmb9PWwcHG1hcmNhbmRy # ZS5sdXJlYXVAcmVkaGF0LmNvbQAKCRDa6OEJdZac5ebjD/43hDmLUGtq3WvEzG7T # A9LjvKJ4bZrJkjwuogMUAAq89L65OcHdnXARgueSwt6Mi0qoakj7F2Ymv2oSw6Gq # 33uspja5PySCGkAs3qQ9lb/zsPFNmXZkhR/XaDGqAFjI24w/QTMq+wwiEuqjVC6P # 2C4VEXxz2Qn+WTQQjzpQ7E7CAUE/grHqflm+5JFICHywjj+oyoa5EnqEXHNlMb2J # b8YVJ3z4SPNkq3VkQMHT0+aVO3+uS0NGxfXxGkVsSTdG1NlvwUr7bSomwZfXiUvP # C0meotfsZTHZCJRtskCvn3kAd3E5EmIjMyDsbhqB0doCLCElV4AlzWSscy1y/GO+ # xm49Kutc+GRx/pztVMGzmC7aJ3Gwa8gKIrY1C/OvO8G2dZrJmTs2ydD4J9mIGxvC # 1p1XeHZi8UOVshBDyAKRovKGzGiRtoC05SvjPOgB58RYGbUfFYHUOah3qYfRRZSw # nPOXiwcrqiIlzkPRXB1ACVLfoZAHWzEFhrGxIKVdHABfwg8Rt9SmJq3JX8ysbKUJ # FUI0/ZExrzGTURWWCm48k2rXZGKG/YSgvdmsSB5QmPEdrrb2jKqp5dmAbg3o/04b # z4A7AatVNfK3tG69/hD1PwAy50q/sbbRUL9ZbBnc4Fnx1xyAOL4LgZ2tMov/jQWE # 1SXLu8GKi4Yt76hUXFn1anqR0A== # =zBkM # -----END PGP SIGNATURE----- # gpg: Signature made Wed 02 Oct 2024 13:32:44 BST # gpg: using RSA key 87A9BD933F87C606D276F62DDAE8E10975969CE5 # gpg: issuer "marcandre.lureau@redhat.com" # gpg: Good signature from "Marc-André Lureau <marcandre.lureau@redhat.com>" [full] # gpg: aka "Marc-André Lureau <marcandre.lureau@gmail.com>" [full] # Primary key fingerprint: 87A9 BD93 3F87 C606 D276 F62D DAE8 E109 7596 9CE5 * tag 'warn-pull-request' of https://gitlab.com/marcandre.lureau/qemu: (22 commits) qom/object: fix -Werror=maybe-uninitialized fsdep/9p: fix -Werror=maybe-uninitialized false-positive block: fix -Werror=maybe-uninitialized false-positive hw/virtio: freeing leaked memory from vhost_svq_get_buf in vhost_svq_poll hw/virtio: fix -Werror=maybe-uninitialized tests: fix -Werror=maybe-uninitialized false-positive target/loongarch: fix -Werror=maybe-uninitialized false-positive linux-user/hppa: fix -Werror=maybe-uninitialized false-positive migration: fix -Werror=maybe-uninitialized false-positive hw/virtio-blk: fix -Werror=maybe-uninitialized false-positive migration: fix -Werror=maybe-uninitialized false-positives block/block-copy: fix -Werror=maybe-uninitialized false-positive hw/sdhci: fix -Werror=maybe-uninitialized false-positive hw/vhost-scsi: fix -Werror=maybe-uninitialized hw/ahci: fix -Werror=maybe-uninitialized false-positive block/stream: fix -Werror=maybe-uninitialized false-positives block/mirror: fix -Werror=maybe-uninitialized false-positive block/mirror: fix -Werror=maybe-uninitialized false-positive nbd: fix -Werror=maybe-uninitialized false-positive hw/qxl: fix -Werror=maybe-uninitialized false-positives ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-10-02Merge tag 'pull-riscv-to-apply-20241002' of ↵Peter Maydell11-17/+160
https://github.com/alistair23/qemu into staging RISC-V PR for 9.2 * Add a property to set vl to ceil(AVL/2) * Enable numamem testing for RISC-V * Consider MISA bit choice in implied rule * Fix the za64rs priv spec requirements * Enable Bit Manip for OpenTitan Ibex CPU * Fix the group bit setting of AIA with KVM * Stop timer with infinite timecmp * Add 'fcsr' register to QEMU log as a part of F extension * Fix riscv64 build on musl libc * Add preliminary textra trigger CSR functions * RISC-V bsd-user support * Respect firmware ELF entry point * Add Svvptc extension support * Fix masking of rv32 physical address * Fix linking problem with semihosting disabled * Fix IMSIC interrupt state updates # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEEaukCtqfKh31tZZKWr3yVEwxTgBMFAmb83lYACgkQr3yVEwxT # gBNndBAAmh66yWt9TeTHlQ/rgBhx2nUMBbfICBWQyNGvPlslffwrNoLkh8jpkuiP # PD0RQArAAGeM09cgCZCu14JzIBmmNiGgUxsUnqOZvUw18uIlLFlpt/tiT7iGw/Xb # pfI7waF66/FPXBErY2yiw9/RGQLlkiGNBC9FNYrD/kCahf9MSIobv85tOgSQ2qjH # nOJ+UBN0TQ1x0Z5lJMj9Pzl1WDvelRnCkYI5nXg1heKG73Hm7GmHt99QpTV2Okqn # T3jFzEfMTQeHO4nC/X2pbaesE62K+mTg/FZpId2iV8lMCSm1zKof+xJ4boKM9RB2 # 0HjXAT+MveLuLUNtgfbV9C+VgU25M+wnfy5tH0l801Y/Gez8Q1fbK2uykuiyiUSy # MNNk/KzmOYuffwItuyeL3mmWHXsN+izUIeMmMxfL9X9nssZXRsrDXc+MByS7w0fk # QOeZmXHTxXwxFymr0t0DLK2eKEG6cqQty1KWp6iLx3uwnMTGo+576P41Q+boj64s # VllWzmuR0Ta0xuSR4sDvEFCO7OCFEgVdn1j0FvhRFskPEDrbQgXRLq8i3awtU6z1 # NIh+A30XeK+EZLv0sEje6gav5lZHWMfAeCOKJstVzOl8+NQibuKTUrsqLgTrBK6K # plw8qwvZYjSnYErzHfywlq9ArufIvOHYcx9Nb76tLNy9E+y01yo= # =15Hm # -----END PGP SIGNATURE----- # gpg: Signature made Wed 02 Oct 2024 06:47:02 BST # gpg: using RSA key 6AE902B6A7CA877D6D659296AF7C95130C538013 # gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 6AE9 02B6 A7CA 877D 6D65 9296 AF7C 9513 0C53 8013 * tag 'pull-riscv-to-apply-20241002' of https://github.com/alistair23/qemu: (35 commits) bsd-user: Add RISC-V 64-bit Target Configuration and Debug XML Files bsd-user: Implement set_mcontext and get_ucontext_sigreturn for RISCV bsd-user: Implement 'get_mcontext' for RISC-V bsd-user: Implement RISC-V signal trampoline setup functions bsd-user: Define RISC-V signal handling structures and constants bsd-user: Add generic RISC-V64 target definitions bsd-user: Define RISC-V system call structures and constants bsd-user: Define RISC-V VM parameters and helper functions bsd-user: Add RISC-V thread setup and initialization support bsd-user: Implement RISC-V sysarch system call emulation bsd-user: Add RISC-V signal trampoline setup function bsd-user: Define RISC-V register structures and register copying bsd-user: Add RISC-V ELF definitions and hardware capability detection bsd-user: Implement RISC-V TLS register setup bsd-user: Implement RISC-V CPU register cloning and reset functions bsd-user: Add RISC-V CPU execution loop and syscall handling bsd-user: Implement RISC-V CPU initialization and main loop hw/intc: riscv-imsic: Fix interrupt state updates. target/riscv/cpu_helper: Fix linking problem with semihosting disabled target/riscv32: Fix masking of physical address ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-10-02target/loongarch: fix -Werror=maybe-uninitialized false-positiveMarc-André Lureau1-12/+14
../target/loongarch/gdbstub.c:55:20: error: ‘val’ may be used uninitialized [-Werror=maybe-uninitialized] 55 | return gdb_get_reg32(mem_buf, val); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ ../target/loongarch/gdbstub.c:39:18: note: ‘val’ was declared here 39 | uint64_t val; Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Vladimir Sementsov-Ogievskiy <vsementsov@yandex-team.ru>
2024-10-02kvm/i386: fix return values of is_host_cpu_intel()Ani Sinha2-4/+4
is_host_cpu_intel() should return TRUE if the host cpu in Intel based, otherwise it should return FALSE. Currently, it returns zero (FALSE) when the host CPU is INTEL and non-zero otherwise. Fix the function so that it agrees more with the semantics. Adjust the calling logic accordingly. RAPL needs Intel host cpus. If the host CPU is not Intel baseed, we should report error. Signed-off-by: Ani Sinha <anisinha@redhat.com> Link: https://lore.kernel.org/r/20240903080004.33746-1-anisinha@redhat.com [While touching the code remove too many spaces from the second part of the error. - Paolo] Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2024-10-02kvm/i386: make kvm_filter_msr() and related definitions private to kvm moduleAni Sinha2-12/+11
kvm_filer_msr() is only used from i386 kvm module. Make it static so that its easy for developers to understand that its not used anywhere else. Same for QEMURDMSRHandler, QEMUWRMSRHandler and KVMMSRHandlers definitions. CC: philmd@linaro.org Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Ani Sinha <anisinha@redhat.com> Link: https://lore.kernel.org/r/20240903140045.41167-1-anisinha@redhat.com [Make struct unnamed. - Paolo] Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2024-10-02target/i386: Raise the highest index value used for any VMCS encodingLei Wang2-1/+9
Because the index value of the VMCS field encoding of FRED injected-event data (one of the newly added VMCS fields for FRED transitions), 0x52, is larger than any existing index value, raise the highest index value used for any VMCS encoding to 0x52. Because the index value of the VMCS field encoding of Secondary VM-exit controls, 0x44, is larger than any existing index value, raise the highest index value used for any VMCS encoding to 0x44. Co-developed-by: Xin Li <xin3.li@intel.com> Signed-off-by: Xin Li <xin3.li@intel.com> Signed-off-by: Lei Wang <lei4.wang@intel.com> Signed-off-by: Xin Li (Intel) <xin@zytor.com> Link: https://lore.kernel.org/r/20240807081813.735158-4-xin@zytor.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2024-10-02target/i386: Add VMX control bits for nested FRED supportXin Li (Intel)1-2/+2
Add definitions of 1) VM-exit activate secondary controls bit 2) VM-entry load FRED bit which are required to enable nested FRED. Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Signed-off-by: Xin Li (Intel) <xin@zytor.com> Link: https://lore.kernel.org/r/20240807081813.735158-3-xin@zytor.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2024-10-02target/i386: Delete duplicated macro definition CR4_FRED_MASKXin Li (Intel)1-6/+0
Macro CR4_FRED_MASK is defined twice, delete one. Signed-off-by: Xin Li (Intel) <xin@zytor.com> Link: https://lore.kernel.org/r/20240807081813.735158-2-xin@zytor.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2024-10-02target/riscv/cpu_helper: Fix linking problem with semihosting disabledThomas Huth2-2/+4
If QEMU has been configured with "--without-default-devices", the build is currently failing with: /usr/bin/ld: libqemu-riscv32-softmmu.a.p/target_riscv_cpu_helper.c.o: in function `riscv_cpu_do_interrupt': .../qemu/target/riscv/cpu_helper.c:1678:(.text+0x2214): undefined reference to `do_common_semihosting' We always want semihosting to be enabled if TCG is available, so change the "imply" statements in the Kconfig file to "select", and make sure to avoid calling into do_common_semihosting() if TCG is not available. Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20240906094858.718105-1-thuth@redhat.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-10-02target/riscv32: Fix masking of physical addressAndrew Jones1-3/+3
C doesn't extend the sign bit for unsigned types since there isn't a sign bit to extend. This means a promotion of a u32 to a u64 results in the upper 32 bits of the u64 being zero. If that result is then used as a mask on another u64 the upper 32 bits will be cleared. rv32 physical addresses may be up to 34 bits wide, so we don't want to clear the high bits while page aligning the address. The fix is to use hwaddr for the mask, which, even on rv32, is 64-bits wide. Fixes: af3fc195e3c8 ("target/riscv: Change the TLB page size depends on PMP entries.") Signed-off-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20240909083241.43836-2-ajones@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-10-02target: riscv: Add Svvptc extension supportAlexandre Ghiti2-0/+3
The Svvptc extension describes a uarch that does not cache invalid TLB entries: that's the case for qemu so there is nothing particular to implement other than the introduction of this extension. Since qemu already exposes Svvptc behaviour, let's enable it by default since it allows to drastically reduce the number of sfence.vma emitted by S-mode. Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20240828083651.203861-1-alexghiti@rivosinc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-10-02target/riscv: Add textra matching condition for the triggersAlvin Chang2-1/+47
According to RISC-V Debug specification, the optional textra32 and textra64 trigger CSRs can be used to configure additional matching conditions for the triggers. For example, if the textra.MHSELECT field is set to 4 (mcontext), this trigger will only match or fire if the low bits of mcontext/hcontext equal textra.MHVALUE field. This commit adds the aforementioned matching condition as common trigger matching conditions. Currently, the only legal values of textra.MHSELECT are 0 (ignore) and 4 (mcontext). When textra.MHSELECT is 0, we pass the checking. When textra.MHSELECT is 4, we compare textra.MHVALUE with mcontext CSR. The remaining fields, such as textra.SBYTEMASK, textra.SVALUE, and textra.SSELECT, are hardwired to zero for now. Thus, we skip checking them here. Signed-off-by: Alvin Chang <alvinga@andestech.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20240826024657.262553-3-alvinga@andestech.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-10-02target/riscv: Preliminary textra trigger CSR writting supportAlvin Chang2-6/+73
This commit allows program to write textra trigger CSR for type 2, 3, 6 triggers. In this preliminary patch, the textra.MHVALUE and the textra.MHSELECT fields are allowed to be configured. Other fields, such as textra.SBYTEMASK, textra.SVALUE, and textra.SSELECT, are hardwired to zero for now. For textra.MHSELECT field, the only legal values are 0 (ignore) and 4 (mcontext). Writing 1~3 into textra.MHSELECT will be changed to 0, and writing 5~7 into textra.MHSELECT will be changed to 4. This behavior is aligned to RISC-V SPIKE simulator. Signed-off-by: Alvin Chang <alvinga@andestech.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20240826024657.262553-2-alvinga@andestech.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-10-02target/riscv/cpu.c: Add 'fcsr' register to QEMU log as a part of F extensionMaria Klauchek1-0/+6
FCSR is a part of F extension. Print it to log if FPU option is enabled. Signed-off-by: Maria Klauchek <m.klauchek@syntacore.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20240902103433.18424-1-m.klauchek@syntacore.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-10-02target/riscv: Stop timer with infinite timecmpAndrew Jones1-0/+1
While the spec doesn't state it, setting timecmp to UINT64_MAX is another way to stop a timer, as it's considered setting the next timer event to occur at infinity. And, even if the time CSR does eventually reach UINT64_MAX, the very next tick will bring it back to zero, once again less than timecmp. For this reason riscv_timer_write_timecmp() special cases UINT64_MAX. However, if a previously set timecmp has not yet expired, then setting timecmp to UINT64_MAX to disable / stop it would not work, as the special case left the previous QEMU timer active, which would then still deliver an interrupt at that previous timecmp time. Ensure the stopped timer will not still deliver an interrupt by also deleting the QEMU timer in the UINT64_MAX special case. Fixes: ae0edf2188b3 ("target/riscv: No need to re-start QEMU timer when timecmp == UINT64_MAX") Signed-off-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20240829084002.1805006-2-ajones@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-10-02target/riscv/kvm: Fix the group bit setting of AIAAndrew Jones1-1/+3
Just as the hart bit setting of the AIA should be calculated as ceil(log2(max_hart_id + 1)) the group bit setting should be calculated as ceil(log2(max_group_id + 1)). The hart bits are implemented by passing max_hart_id to find_last_bit() and adding one to the result. Do the same for the group bit setting. Signed-off-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20240821075040.498945-2-ajones@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-10-02target: riscv: Enable Bit Manip for OpenTitan Ibex CPUAlistair Francis1-0/+5
The OpenTitan Ibex CPU now supports the the Zba, Zbb, Zbc and Zbs bit-manipulation sub-extensions ratified in v.1.0.0 of the RISC-V Bit- Manipulation ISA Extension, so let's enable them in QEMU as well. 1: https://github.com/lowRISC/opentitan/pull/9748 Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20240823003231.3522113-1-alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-10-02target/riscv: fix za64rs enablingVladimir Isaev1-1/+1
za64rs requires priv 1.12 when enabled by priv 1.11. This fixes annoying warning: warning: disabling za64rs extension for hart 0x00000000 because privilege spec version does not match on priv 1.11 CPUs. Fixes: 68c9e54beae8 ("target/riscv: do not enable all named features by default") Signed-off-by: Vladimir Isaev <vladimir.isaev@syntacore.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20240823063431.17474-1-vladimir.isaev@syntacore.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-10-02target/riscv/tcg/tcg-cpu.c: consider MISA bit choice in implied ruleDaniel Henrique Barboza1-3/+10
Gitlab issue [1] reports a misleading error when trying to run a 'rv64' cpu with 'zfinx' and without 'f': $ ./build/qemu-system-riscv64 -nographic -M virt -cpu rv64,zfinx=true,f=false qemu-system-riscv64: Zfinx cannot be supported together with F extension The user explicitly disabled F and the error message mentions a conflict with Zfinx and F. The problem isn't the error reporting, but the logic used when applying the implied ZFA rule that enables RVF unconditionally, without honoring user choice (i.e. keep F disabled). Change cpu_enable_implied_rule() to check if the user deliberately disabled a MISA bit. In this case we shouldn't either re-enable the bit nor apply any implied rules related to it. After this change the error message now shows: $ ./build/qemu-system-riscv64 -nographic -M virt -cpu rv64,zfinx=true,f=false qemu-system-riscv64: Zfa extension requires F extension Disabling 'zfa': $ ./build/qemu-system-riscv64 -nographic -M virt -cpu rv64,zfinx=true,f=false,zfa=false qemu-system-riscv64: D extension requires F extension And finally after disabling 'd': $ ./build/qemu-system-riscv64 -nographic -M virt -cpu rv64,zfinx=true,f=false,zfa=false,d=false (OpenSBI boots ...) [1] https://gitlab.com/qemu-project/qemu/-/issues/2486 Cc: Frank Chang <frank.chang@sifive.com> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2486 Fixes: 047da861f9 ("target/riscv: Introduce extension implied rule helpers") Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20240824173338.316666-1-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-10-02target/riscv: Add a property to set vl to ceil(AVL/2)Jason Chien3-0/+4
RVV spec allows implementations to set vl with values within [ceil(AVL/2),VLMAX] when VLMAX < AVL < 2*VLMAX. This commit adds a property "rvv_vl_half_avl" to enable setting vl = ceil(AVL/2). This behavior helps identify compiler issues and bugs. Signed-off-by: Jason Chien <jason.chien@sifive.com> Reviewed-by: Frank Chang <frank.chang@sifive.com> Message-ID: <20240722175004.23666-1-jason.chien@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-10-01target/arm: Avoid target_ulong for physical address lookupsArd Biesheuvel2-10/+10
target_ulong is typedef'ed as a 32-bit integer when building the qemu-system-arm target, and this is smaller than the size of an intermediate physical address when LPAE is being used. Given that Linux may place leaf level user page tables in high memory when built for LPAE, the kernel will crash with an external abort as soon as it enters user space when running with more than ~3 GiB of system RAM. So replace target_ulong with vaddr in places where it may carry an address value that is not representable in 32 bits. Fixes: f3639a64f602ea ("target/arm: Use softmmu tlbs for page table walking") Cc: qemu-stable@nongnu.org Reported-by: Arnd Bergmann <arnd@arndb.de> Tested-by: Arnd Bergmann <arnd@arndb.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Message-id: 20240927071051.1444768-1-ardb+git@google.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-09-28Merge tag 'pull-request-2024-09-25' of https://gitlab.com/thuth/qemu into ↵Peter Maydell6-11/+7
staging * Convert more Avocado tests to the new functional test framework * Clean up assert() statements, use g_assert_not_reached() when possible * Improve output of the gitlab CI jobs # -----BEGIN PGP SIGNATURE----- # # iQJFBAABCAAvFiEEJ7iIR+7gJQEY8+q5LtnXdP5wLbUFAmbz7xgRHHRodXRoQHJl # ZGhhdC5jb20ACgkQLtnXdP5wLbWm6A//eVn+tzyyKCX/xdXlf7XyVpezvRpTFPOS # HyO0WMkCf2kGmu6qYKx/fDZg86opdQzPLH2gPkuVrGOMZ0Z2630DjH0jNih8lL9Q # J1oRX5YlU92chlzNmq59WB/j9CKd91ILtOoaPBuZkDob57yGEYVzCPqetVvF7L2+ # +rbnccrNPumGJFt035fxUGiGfgsmp28MHQzDwQdyr38uGjyNlqvqidfC8Vj1qzqP # B7HvhGB/vkF0eHaanMt2el/ZuLKf+qeCi//F/CiXGMYnuKXyShA/Db6xvMElw1jB # aQdwphP71IO+cxjJLaNjDHKGFstArsM/E21qlaSTBi+FTmPiwVULpVTiBmWsjhOh # /klpdgRHf0hL2MciYKyOWgjlTocx3rEKjCTe2U5tpta9fp9CrlgMQotjDZIbohGI # ULNahrW3Zmg4EmXDApfhYMXsQsSgWas9QSkmxzJzDp0VC7tf2Oq7RxeySrlw9MCx # OG2qQY+rNcJ3NnpATjfAJpT1kg/IahDOCNHfLEaj1u13XVQIthVADvHwy5WxbwRP # mwp3V9e9sUoznkM2eV646lzmkMim/WdYBF0YpT7eBs80+GoXZ0thx9IqWmwzX/ox # rndBczVN+RY6PydJP40yljdvS7ArRT73wHqL6yKHfDpvFc4/p5mxTWwLQ3yJbXbE # T3I+wtgfBU8= # =FH7b # -----END PGP SIGNATURE----- # gpg: Signature made Wed 25 Sep 2024 12:08:08 BST # gpg: using RSA key 27B88847EEE0250118F3EAB92ED9D774FE702DB5 # gpg: issuer "thuth@redhat.com" # gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" [full] # gpg: aka "Thomas Huth <thuth@redhat.com>" [full] # gpg: aka "Thomas Huth <huth@tuxfamily.org>" [full] # gpg: aka "Thomas Huth <th.huth@posteo.de>" [unknown] # Primary key fingerprint: 27B8 8847 EEE0 2501 18F3 EAB9 2ED9 D774 FE70 2DB5 * tag 'pull-request-2024-09-25' of https://gitlab.com/thuth/qemu: (44 commits) .gitlab-ci.d: Make separate collapsible log sections for build and test .gitlab-ci.d: Split build and test in cross build job templates scripts/checkpatch.pl: emit error when using assert(false) tests/qtest: remove return after g_assert_not_reached() qom: remove return after g_assert_not_reached() qobject: remove return after g_assert_not_reached() migration: remove return after g_assert_not_reached() hw/ppc: remove return after g_assert_not_reached() hw/pci: remove return after g_assert_not_reached() hw/net: remove return after g_assert_not_reached() hw/hyperv: remove return after g_assert_not_reached() include/qemu: remove return after g_assert_not_reached() tcg/loongarch64: remove break after g_assert_not_reached() fpu: remove break after g_assert_not_reached() target/riscv: remove break after g_assert_not_reached() target/arm: remove break after g_assert_not_reached() hw/tpm: remove break after g_assert_not_reached() hw/scsi: remove break after g_assert_not_reached() hw/net: remove break after g_assert_not_reached() hw/acpi: remove break after g_assert_not_reached() ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-09-27Merge tag 'pull-tcg-20240922' of https://gitlab.com/rth7680/qemu into stagingPeter Maydell1-1/+1
target/ppc: Fix lxvx/stxvx facility check linux-user: update syscall_nr.h to Linux v6.10 linux-user: update syscall.tbl to Linux v6.11 tcg: Fix iteration step in 32-bit gvec operation tcg: Propagate new TCGOp to add_as_label_use tcg/*: Do not expand cmp_vec, cmpsel_vec early tcg/optimize: Fold movcond with true and false values identical tcg/optimize: Optimize cmp_vec and cmpsel_vec tcg/optimize: Optimize bitsel_vec tcg/i386: Optimize cmpsel with constant 0 operand 3. tcg/i386: Implement cmp_vec with avx512 insns tcg/i386: Implement cmpsel_vec with avx512 insns tcg/i386: Implement vector TST{EQ,NE} for avx512 tcg/ppc: Implement cmpsel_vec and optimize with constant 0/-1 arguments tcg/s390x: Implement cmpsel_vec and optimize with constant 0/-1 arguments # -----BEGIN PGP SIGNATURE----- # # iQFQBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmbwBsIdHHJpY2hhcmQu # aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV/bzwf40V8fsRhfc8u/k2Xw # +bXyfyX7ydgB+82YoO71+Wy15ntmYmbL/6O9kGuJXWX8HRDrAR8Js9zDgveysw5m # m/EG+XAbVjYhjaoaaz2nfr+5auQoos9NoCji3s3UJln6sCuZ2Enl0DTFluoHZfgr # /YVAghJ4dwH0hfzO9kmsKmJ9I19HugMMN4dNvEcjQyDDUhgGGjkUaRtGNxwuiwuf # ArL2XhFauXgloryDmpUKQ0BJJ0t8rdPlaRJ8dHqJUnJwav0TW3QVXbrs8gOkmmbg # 9plYTC9DlTguQobvapCDVjiGy/6yuSF/AUpcdQbTRtTi3BrzhTydfLlOtI64GtaQ # OBKd # =ID/g # -----END PGP SIGNATURE----- # gpg: Signature made Sun 22 Sep 2024 13:00:02 BST # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * tag 'pull-tcg-20240922' of https://gitlab.com/rth7680/qemu: (31 commits) linux-user: update syscall.tbl to Linux v6.11 linux-user,loongarch: move to syscalltbl file linux-user,hexagon: move to syscalltbl file linux-user,riscv: move to syscalltbl file linux-user,openrisc: move to syscalltbl file linux-user,aarch64: move to syscalltbl file linux-user: update syscall.tbl to Linux v6.10 linux-user, mips: update syscall-args-o32.c.inc to Linux v6.10 linux-user: update syscall_nr.h to Linux v6.10 target/ppc: Fix lxvx/stxvx facility check tcg/s390x: Optimize cmpsel with constant 0/-1 arguments tcg/s390x: Implement cmpsel_vec tcg/ppc: Optimize cmpsel with constant 0/-1 arguments tcg/ppc: Implement cmpsel_vec tcg/i386: Implement vector TST{EQ,NE} for avx512 tcg/i386: Implement cmpsel_vec with avx512 insns tcg/i386: Add predicate parameters to tcg_out_evex_opc tcg/i386: Implement cmp_vec with avx512 insns tcg/i386: Optimize cmpsel with constant 0 operand 3. tcg/optimize: Optimize bitsel_vec ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-09-24target/riscv: remove break after g_assert_not_reached()Pierrick Bouvier2-3/+0
This patch is part of a series that moves towards a consistent use of g_assert_not_reached() rather than an ad hoc mix of different assertion mechanisms. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-ID: <20240919044641.386068-23-pierrick.bouvier@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2024-09-24target/arm: remove break after g_assert_not_reached()Pierrick Bouvier1-1/+0
This patch is part of a series that moves towards a consistent use of g_assert_not_reached() rather than an ad hoc mix of different assertion mechanisms. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-ID: <20240919044641.386068-22-pierrick.bouvier@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2024-09-24target/i386/kvm: replace assert(false) with g_assert_not_reached()Pierrick Bouvier1-2/+2
This patch is part of a series that moves towards a consistent use of g_assert_not_reached() rather than an ad hoc mix of different assertion mechanisms. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-ID: <20240919044641.386068-15-pierrick.bouvier@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2024-09-24target/ppc: replace assert(0) with g_assert_not_reached()Pierrick Bouvier2-5/+5
This patch is part of a series that moves towards a consistent use of g_assert_not_reached() rather than an ad hoc mix of different assertion mechanisms. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-ID: <20240919044641.386068-7-pierrick.bouvier@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2024-09-22target/ppc: Fix lxvx/stxvx facility checkFabiano Rosas1-1/+1
The XT check for the lxvx/stxvx instructions is currently inverted. This was introduced during the move to decodetree. >From the ISA: Chapter 7. Vector-Scalar Extension Facility Load VSX Vector Indexed X-form lxvx XT,RA,RB if TX=0 & MSR.VSX=0 then VSX_Unavailable() if TX=1 & MSR.VEC=0 then Vector_Unavailable() ... Let XT be the value 32×TX + T. The code currently does the opposite: if (paired || a->rt >= 32) { REQUIRE_VSX(ctx); } else { REQUIRE_VECTOR(ctx); } This was already fixed for lxv/stxv at commit "2cc0e449d1 (target/ppc: Fix lxv/stxv MSR facility check)", but the indexed forms were missed. Cc: qemu-stable@nongnu.org Fixes: 70426b5bb7 ("target/ppc: moved stxvx and lxvx from legacy to decodtree") Signed-off-by: Fabiano Rosas <farosas@suse.de> Reviewed-by: Claudio Fontana <cfontana@suse.de> Acked-by: Ilya Leoshkevich <iii@linux.ibm.com> Reviewed-by: Fabiano Rosas <farosas@suse.de> Message-ID: <20240911141651.6914-1-farosas@suse.de> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-09-20license: Update deprecated SPDX tag GPL-2.0+ to GPL-2.0-or-laterPhilippe Mathieu-Daudé2-2/+2
The 'GPL-2.0+' license identifier has been deprecated since license list version 2.0rc2 [1] and replaced by the 'GPL-2.0-or-later' [2] tag. [1] https://spdx.org/licenses/GPL-2.0+.html [2] https://spdx.org/licenses/GPL-2.0-or-later.html Mechanical patch running: $ sed -i -e s/GPL-2.0+/GPL-2.0-or-later/ \ $(git grep -lP 'SPDX-License-Identifier: \W+GPL-2.0\+[ $]' \ | egrep -v '^linux-headers|^include/standard-headers') Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2024-09-20license: Update deprecated SPDX tag LGPL-2.0+ to LGPL-2.0-or-laterPhilippe Mathieu-Daudé12-12/+12
The 'LGPL-2.0+' license identifier has been deprecated since license list version 2.0rc2 [1] and replaced by the 'LGPL-2.0-or-later' [2] tag. [1] https://spdx.org/licenses/LGPL-2.0+.html [2] https://spdx.org/licenses/LGPL-2.0-or-later.html Mechanical patch running: $ sed -i -e s/LGPL-2.0+/LGPL-2.0-or-later/ \ $(git grep -l 'SPDX-License-Identifier: LGPL-2.0+$') Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2024-09-20target/hexagon: Rename macros.inc -> macros.h.incPhilippe Mathieu-Daudé4-4/+4
Since commits 139c1837db ("meson: rename included C source files to .c.inc") and 0979ed017f ("meson: rename .inc.h files to .h.inc"), EMU standard procedure for included header files is to use *.h.inc. Besides, since commit 6a0057aa22 ("docs/devel: make a statement about includes") this is documented in the Coding Style: If you do use template header files they should be named with the ``.c.inc`` or ``.h.inc`` suffix to make it clear they are being included for expansion. Therefore rename "macros.inc" as "macros.h.inc". Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Brian Cain <bcain@quicinc.com> Reviewed-by: Anton Johansson <anjo@rev.ng> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2024-09-20mark <zlib.h> with for-crc32 in a consistent mannerMichael Tokarev3-3/+3
in many cases, <zlib.h> is only included for crc32 function, and in some of them, there's a comment saying that, but in a different way. In one place (hw/net/rtl8139.c), there was another #include added between the comment and <zlib.h> include. Make all such comments to be on the same line as #include, make it consistent, and also add a few missing comments, including hw/nvram/mac_nvram.c which uses adler32 instead. There's no code changes. Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2024-09-19target/arm: Correct ID_AA64ISAR1_EL1 value for neoverse-v1Peter Maydell1-1/+1
The Neoverse-V1 TRM is a bit confused about the layout of the ID_AA64ISAR1_EL1 register, and so its table 3-6 has the wrong value for this ID register. Trust instead section 3.2.74's list of which fields are set. This means that we stop incorrectly reporting FEAT_XS as present, and now report the presence of FEAT_BF16. Cc: qemu-stable@nongnu.org Reported-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240917161337.3012188-1-peter.maydell@linaro.org
2024-09-19target/arm: Convert scalar [US]QSHRN, [US]QRSHRN, SQSHRUN to decodetreeRichard Henderson2-127/+63
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240912024114.1097832-30-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-09-19target/arm: Convert vector [US]QSHRN, [US]QRSHRN, SQSHRUN to decodetreeRichard Henderson2-14/+186
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240912024114.1097832-29-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-09-19target/arm: Convert SQSHL, UQSHL, SQSHLU (immediate) to decodetreeRichard Henderson2-131/+128
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240912024114.1097832-28-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-09-19target/arm: Widen NeonGenNarrowEnvFn return to 64 bitsRichard Henderson5-78/+93
While these functions really do return a 32-bit value, widening the return type means that we need do less marshalling between TCG types. Remove NeonGenNarrowEnvFn typedef; add NeonGenOne64OpEnvFn. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20240912024114.1097832-27-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-09-19target/arm: Convert VQSHL, VQSHLU to gvecRichard Henderson6-110/+94
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240912024114.1097832-26-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-09-19target/arm: Convert handle_scalar_simd_shli to decodetreeRichard Henderson2-35/+13
This includes SHL and SLI. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240912024114.1097832-25-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
generated by cgit v1.1 at 2025-02-07 08:09:26 +0000