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2019-02-18target/ppc: convert vadd*s and vsub*s to vector operationsRichard Henderson3-38/+61
2019-02-18target/ppc: Split out VSCR_SAT to a vector fieldRichard Henderson2-4/+11
2019-02-18target/ppc: Add set_vscr_satRichard Henderson1-12/+17
2019-02-18target/ppc: Use mtvscr/mfvscr for vmstateRichard Henderson1-3/+41
2019-02-18target/ppc: Add helper_mfvscrRichard Henderson5-3/+10
2019-02-18target/ppc: Remove vscr_nj and vscr_satRichard Henderson1-2/+0
2019-02-18target/ppc: Use helper_mtvscr for reset and gdbRichard Henderson1-3/+2
2019-02-18target/ppc: Pass integer to helper_mtvscrRichard Henderson3-8/+17
2019-02-18target/ppc: convert xxsel to vector operationsRichard Henderson1-28/+27
2019-02-18target/ppc: convert xxspltw to vector operationsRichard Henderson1-25/+11
2019-02-18target/ppc: convert xxspltib to vector operationsRichard Henderson1-8/+5
2019-02-18target/ppc: convert VSX logical operations to vector operationsRichard Henderson1-26/+17
2019-02-18target/ppc: convert vsplt[bhw] to use vector operationsRichard Henderson3-41/+27
2019-02-18target/ppc: convert vspltis[bhw] to use vector operationsRichard Henderson3-46/+8
2019-02-18target/ppc: convert vaddu[b,h,w,d] and vsubu[b,h,w,d] over to use vector oper...Mark Cave-Ayland3-23/+8
2019-02-18target/ppc: convert VMX logical instructions to use vector operationsMark Cave-Ayland2-31/+17
2019-02-17target/ppc: Disable ISA 2.06 PM instructions on POWER9Benjamin Herrenschmidt1-1/+1
2019-02-17ppc: fix crash during branch steppingRoman Kapl1-22/+15
2019-02-17target/ppc: Remove some #if 0'ed codeBenjamin Herrenschmidt2-24/+0
2019-02-17target/ppc: Fix msync to do what hardware doesBALATON Zoltan1-3/+8
2019-02-17target/ppc: Enable reporting of SPRs to GDBFabiano Rosas4-2/+130
2019-02-15target/arm: Add missing clear_tail callsRichard Henderson1-0/+2
2019-02-15target/arm: Use vector operations for saturationRichard Henderson5-44/+331
2019-02-15target/arm: Split out FPSCR.QC to a vector fieldRichard Henderson4-7/+21
2019-02-15target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR]Richard Henderson1-7/+8
2019-02-15target/arm: Split out flags setting from vfp comparesRichard Henderson1-18/+27
2019-02-15target/arm: Fix arm_cpu_dump_state vs FPSCRRichard Henderson1-1/+1
2019-02-15target/arm: Fix vfp_gdb_get/set_reg vs FPSCRRichard Henderson1-2/+2
2019-02-15target/arm: Remove neon min/max helpersRichard Henderson2-24/+0
2019-02-15target/arm: Use tcg integer min/max primitives for neonRichard Henderson1-4/+4
2019-02-15target/arm: Use vector minmax expanders for aarch32Richard Henderson1-6/+19
2019-02-15target/arm: Use vector minmax expanders for aarch64Richard Henderson1-21/+14
2019-02-15target/arm: Rely on optimization within tcg_gen_gvec_orRichard Henderson3-19/+5
2019-02-15arm: Allow system registers for KVM guests to be changed by QEMU codePeter Maydell5-22/+38
2019-02-15target/arm: expose remaining CPUID registers as RAZAlex Bennée2-3/+26
2019-02-15target/arm: expose MPIDR_EL1 to userspaceAlex Bennée1-7/+14
2019-02-15target/arm: expose CPUID registers to userspaceAlex Bennée2-0/+80
2019-02-15target/arm: relax permission checks for HWCAP_CPUID registersAlex Bennée2-1/+17
2019-02-15target/arm: Fix int128_make128 lo, hi order in paired_cmpxchg64_beCatherine Ho1-2/+2
2019-02-15target/arm: Implement HACR_EL2Peter Maydell1-0/+6
2019-02-15target/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTRAaron Lindsay OS1-4/+4
2019-02-14target/mips: introduce MTTCG-enabled buildsAleksandar Markovic1-0/+2
2019-02-14target/mips: hold BQL in mips_vpe_wake()Goran Ferenc1-0/+3
2019-02-14hw/mips_int: hold BQL for all interrupt requestsAleksandar Markovic1-18/+3
2019-02-14target/mips: reimplement SC instruction emulation and use cmpxchgLeon Alrae5-118/+44
2019-02-14target/mips: compare virtual addresses in LL/SC sequenceLeon Alrae4-18/+25
2019-02-14Merge remote-tracking branch 'remotes/palmer/tags/riscv-for-master-4.0-sf1' i...Peter Maydell8-106/+394
2019-02-12target/hppa: fix dcor instructionSven Schnelle1-1/+1
2019-02-12target/hppa: Fix addition '</<=' conditionsSven Schnelle1-36/+57
2019-02-12target/hppa: Rearrange log conditionsRichard Henderson1-7/+49