aboutsummaryrefslogtreecommitdiff
path: root/target
AgeCommit message (Expand)AuthorFilesLines
2020-12-11Merge remote-tracking branch 'remotes/bonzini-gitlab/tags/for-upstream' into ...Peter Maydell14-68/+632
2020-12-10i386/cpu: Make the Intel PT LIP feature configurableLuwei Kang2-1/+34
2020-12-10sev: add sev-inject-launch-secretTobin Feldman-Fitzthum4-0/+78
2020-12-10s390x: do not use ram_size globalPaolo Bonzini3-5/+12
2020-12-10m68k: do not use ram_size globalPaolo Bonzini1-2/+3
2020-12-10arm: do not use ram_size globalPaolo Bonzini1-1/+2
2020-12-10WHPX: support for the kernel-irqchip on/offSunil Muthuswamy5-35/+543
2020-12-10target/i386: seg_helper: Correct segment selector nullification in the RET/IR...Bin Meng1-1/+4
2020-12-10target/i386: Support up to 32768 CPUs without IRQ remappingDavid Woodhouse3-20/+64
2020-12-10target/i386: fix operand order for PDEP and PEXTPaolo Bonzini1-4/+4
2020-12-10target/arm: Implement M-profile "minimal RAS implementation"Peter Maydell2-0/+18
2020-12-10target/arm: Implement CCR_S.TRD behaviour for SG insnsPeter Maydell1-0/+86
2020-12-10hw/intc/armv7m_nvic: Support v8.1M CCR.TRD bitPeter Maydell1-0/+2
2020-12-10target/arm: Implement new v8.1M VLLDM and VLSTM encodingsPeter Maydell2-1/+26
2020-12-10target/arm: Implement new v8.1M NOCP check for exception returnPeter Maydell1-1/+21
2020-12-10target/arm: In v8.1M, don't set HFSR.FORCED on vector table fetch failuresPeter Maydell1-1/+5
2020-12-10target/arm: For v8.1M, always clear R0-R3, R12, APSR, EPSR on exception entryPeter Maydell1-4/+12
2020-12-10hw/intc/armv7m_nvic: Update FPDSCR masking for v8.1MPeter Maydell2-0/+8
2020-12-10target/arm: Implement FPCXT_S fp system registerPeter Maydell1-0/+58
2020-12-10target/arm: Factor out preserve-fp-state from full_vfp_access_check()Peter Maydell1-18/+27
2020-12-10target/arm: Use new FPCR_NZCV_MASK constantPeter Maydell1-2/+2
2020-12-10target/arm: Implement M-profile FPSCR_nzcvqcPeter Maydell2-0/+40
2020-12-10target/arm: Implement VLDR/VSTR system registerPeter Maydell2-0/+105
2020-12-10target/arm: Move general-use constant expanders up in translate.cPeter Maydell1-21/+25
2020-12-10target/arm: Refactor M-profile VMSR/VMRS handlingPeter Maydell2-11/+168
2020-12-10target/arm: Enforce M-profile VMRS/VMSR register restrictionsPeter Maydell1-1/+4
2020-12-10target/arm: Implement CLRM instructionPeter Maydell2-1/+43
2020-12-10target/arm: Implement VSCCLRM insnPeter Maydell4-11/+111
2020-12-10target/arm: Don't clobber ID_PFR1.Security on M-profile coresPeter Maydell1-1/+1
2020-12-10target/arm: Implement v8.1M PXN extensionPeter Maydell1-1/+6
2020-11-24ppc/translate: Implement lxvwsx opcodeLemonBoy2-0/+31
2020-11-23target/arm: Make SYS_HEAPINFO work with RAM that doesn't start at 0Peter Maydell1-4/+8
2020-11-23target/arm: fix stage 2 page-walks in 32-bit emulationRémi Denis-Courmont1-2/+2
2020-11-18s390/kvm: fix diag318 propagation and reset functionalityCollin Walling5-5/+30
2020-11-18hvf: Fix segment selector formatJessica Clarke1-4/+4
2020-11-18hvf: Gate RDTSCP on CPU_BASED2_RDTSCP, not just CPU_BASED_TSC_OFFSETJessica Clarke1-0/+4
2020-11-17Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20201117'...Peter Maydell1-3/+0
2020-11-17Merge remote-tracking branch 'remotes/huth-gitlab/tags/pull-request-2020-11-1...Peter Maydell1-1/+2
2020-11-17target/openrisc: Remove dead code attempting to check "is timer disabled"Peter Maydell1-3/+0
2020-11-17target/microblaze: Fix possible array out of bounds in mmu_write()AlexChen1-1/+2
2020-11-16target/i386: avoid theoretical leak on MCE injectionPaolo Bonzini1-6/+4
2020-11-16kvm/i386: Set proper nested state format for SVMTom Lendacky1-4/+6
2020-11-15nomaintainer: Fix Lesser GPL version numberChetan Pant5-5/+5
2020-11-15sparc tcg cpus: Fix Lesser GPL version numberChetan Pant12-12/+12
2020-11-15x86 hvf cpus: Fix Lesser GPL version numberChetan Pant17-18/+18
2020-11-15overall/alpha tcg cpus|hppa: Fix Lesser GPL version numberChetan Pant18-18/+18
2020-11-15arm tcg cpus: Fix Lesser GPL version numberChetan Pant30-30/+30
2020-11-15x86 tcg cpus: Fix Lesser GPL version numberChetan Pant21-21/+21
2020-11-15tricore tcg cpus: Fix Lesser GPL version numberChetan Pant1-1/+1
2020-11-15xtensa tcg cpus: Fix Lesser GPL version numberChetan Pant1-1/+1
generated by cgit v1.1 at 2024-08-19 23:05:39 +0000