riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2024-10-30	target/riscv: update `decode_save_opc` to store extra word2	Deepak Gupta	11	-34/+35
2024-10-30	target/riscv: AMO operations always raise store/AMO fault	Deepak Gupta	4	-2/+30
2024-10-30	target/riscv: mmu changes for zicfiss shadow stack protection	Deepak Gupta	2	-14/+53
2024-10-30	target/riscv: tb flag for shadow stack instructions	Deepak Gupta	3	-0/+9
2024-10-30	target/riscv: introduce ssp and enabling controls for zicfiss	Deepak Gupta	6	-0/+111
2024-10-30	target/riscv: Add zicfiss extension	Deepak Gupta	3	-0/+25
2024-10-30	target/riscv: Expose zicfilp extension as a cpu property	Deepak Gupta	1	-0/+1
2024-10-30	target/riscv: zicfilp `lpad` impl and branch tracking	Deepak Gupta	3	-1/+60
2024-10-30	target/riscv: tracking indirect branches (fcfi) for zicfilp	Deepak Gupta	4	-0/+39
2024-10-30	target/riscv: additional code information for sw check	Deepak Gupta	3	-0/+6
2024-10-30	target/riscv: save and restore elp state on priv transitions	Deepak Gupta	3	-0/+72
2024-10-30	target/riscv: Introduce elp state and enabling controls for zicfilp	Deepak Gupta	7	-1/+68
2024-10-30	target/riscv: Add zicfilp extension	Deepak Gupta	3	-0/+7
2024-10-30	target/riscv: expose *envcfg csr and priv to qemu-user as well	Deepak Gupta	2	-4/+10
2024-10-30	target/riscv: Set vtype.vill on CPU reset	Rob Bradford	1	-0/+1
2024-10-30	target/riscv: Add max32 CPU for RV64 QEMU	LIU Zhiwei	2	-5/+8
2024-10-30	target/riscv: Enable RV32 CPU support in RV64 QEMU	TANG Tiancheng	1	-3/+13
2024-10-30	target/riscv: Correct mcause/scause bit width for RV32 in RV64 QEMU	TANG Tiancheng	1	-2/+6
2024-10-30	target/riscv: Detect sxl to set bit width for RV32 in RV64	TANG Tiancheng	1	-5/+12
2024-10-30	target/riscv: Correct SXL return value for RV32 in RV64 QEMU	TANG Tiancheng	1	-1/+4
2024-10-30	target/riscv: Adjust PMP size for no-MMU RV64 QEMU running RV32	TANG Tiancheng	1	-1/+1
2024-10-30	target/riscv/csr.c: Fix an access to VXSAT	Evgenii Prokopiev	1	-2/+2
2024-10-24	Merge tag 'pull-request-2024-10-23' of https://gitlab.com/thuth/qemu into sta...	Peter Maydell	1	-1/+8
2024-10-23	s390x: Rebuild IPLB for SCSI device directly from DIAG308	Jared Rossi	1	-1/+8
2024-10-22	target/i386: Remove ra parameter from ptw_translate	Richard Henderson	1	-9/+9
2024-10-22	target/i386: Use probe_access_full_mmu in ptw_translate	Richard Henderson	1	-6/+4
2024-10-22	target/i386: Walk NPT in guest real mode	Alexander Graf	1	-3/+14
2024-10-18	Merge tag 'pull-error-2024-10-18' of https://repo.or.cz/qemu/armbru into staging	Peter Maydell	1	-32/+27
2024-10-18	target/i386/cpu: Improve errors for out of bounds property values	Markus Armbruster	1	-11/+9
2024-10-18	target/i386/cpu: Avoid mixing signed and unsigned in property setters	Markus Armbruster	1	-24/+21
2024-10-18	Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging	Peter Maydell	10	-441/+526
2024-10-17	target/i386: Use only 16 and 32-bit operands for IN/OUT	Richard Henderson	1	-4/+4
2024-10-17	target/i386/tcg: Use DPL-level accesses for interrupts and call gates	Paolo Bonzini	1	-6/+11
2024-10-17	target/i386: assert that cc_op* and pc_save are preserved	Paolo Bonzini	1	-9/+3
2024-10-17	target/i386: list instructions still in translate.c	Paolo Bonzini	1	-0/+31
2024-10-17	target/i386: do not check PREFIX_LOCK in old-style decoder	Paolo Bonzini	1	-18/+8
2024-10-17	target/i386: convert CMPXCHG8B/CMPXCHG16B to new decoder	Paolo Bonzini	4	-129/+124
2024-10-17	target/i386: decode address before going back to translate.c	Paolo Bonzini	4	-118/+103
2024-10-17	target/i386: convert bit test instructions to new decoder	Paolo Bonzini	4	-158/+183
2024-10-17	Merge tag 'pull-loongarch-20241016' of https://gitlab.com/gaosong/qemu into s...	Peter Maydell	1	-5/+1
2024-10-17	target/i386: Make sure SynIC state is really updated before KVM_RUN	Vitaly Kuznetsov	1	-0/+1
2024-10-17	target/i386: Exclude 'hv-syndbg' from 'hv-passthrough'	Vitaly Kuznetsov	1	-2/+5
2024-10-17	target/i386: Fix conditional CONFIG_SYNDBG enablement	Vitaly Kuznetsov	2	-4/+9
2024-10-17	target/i386: Add support save/load HWCR MSR	Gao Shiyuan	3	-0/+37
2024-10-17	target/i386: Add more features enumerated by CPUID.7.2.EDX	Chao Gao	1	-2/+2
2024-10-17	target/i386: Make invtsc migratable when user sets tsc-khz explicitly	Xiaoyao Li	1	-2/+9
2024-10-17	target/i386: Construct CPUID 2 as stateful iff times > 1	Xiaoyao Li	1	-2/+4
2024-10-17	target/i386: Enable fdp-excptn-only and zero-fcs-fds	Xiaoyao Li	2	-2/+6
2024-10-17	target/i386: Don't construct a all-zero entry for CPUID[0xD 0x3f]	Xiaoyao Li	1	-5/+6
2024-10-16	target/loongarch: Avoid bits shift exceeding width of bool type	Bibo Mao	1	-5/+1